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參數(shù)資料
| 型號： | ZL10310DTV-SOC |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Digital Television DVB-T-On-a-Chip Processor |
| 中文描述： | 數(shù)字電視的DVB - T -上一芯片處理器 |
| 文件頁數(shù)： | 31/40頁 |
| 文件大?。?/td> | 670K |
| 代理商： | ZL10310DTV-SOC |
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Data Sheet
ZL10310/ZL10311
31
Zarlink Semiconductor Inc.
Note 1:
DA_DEEMPHASIS [1:0] have following truth-table: ‘00’ = No emphasis, ‘01’ = 50-15 ms emphasis, ‘10’ = Reserved, ‘11’ =
CCITT J.17
DA_SURMOD[1:0] used to indicate whether Dolby Digital encoded stream has been encoded in Dolby Surround.
DA_LR_CH_CLK (via GP19) is a clock whose phase indicates the presence of left hand or right hand data, and whose rate is
equivalent to fs. Signal routed through to GP14 (not bonded out).
GP00 and GP01 inputs are Latched during Power-up only. Active Low Input at power-up to enable Boot Mode functions.
GP03 and GP17 inputs are Latched at Power-up only.
GP29 XPT_PWM_OUTPUT Compensates for frequency errors in 27MHz external VCXO.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
6.11 Simplified General Purpose Input Output Interface
The Simplified General Purpose Input Output Interface is provided with 8 pins that can be configured as general
purpose I/O bits. As there is only one mapped SGPIO signal mapped to each of the pins, the interface is simple,
with SGPIO inputs monitored using the SGPI input register, and outputs set using the SGPO register.
The Reserved signals are configured as “Big Endian”. This means that DV1_DATA [0] is the Most Significant Bit
(MSB).
GP19
D21
GPIO_19
IO
5V
General Purpose
Input/Output - Bit 19
GPOS Reg Bits 38:39 = '00'
GPT_CAPT0
I 5V
General Purpose Timer -
Capture Timer 0 Input
GPIS1 Reg Bits 38:39 = '01'
DV2_VSYNC
IO
5V
Reserved
GPOS Reg Bits 38:39 = '10',
GPIS2 Reg Bits 38:39 = '01'
SSP_FS
I 5V
Synchronous Serial Port for
Modem - Frame Sync
GPIS2 Reg Bits 28:29 = '01'
DA_LR_CH_CLK
I 5V
I
2
S Digital Audio Left-Right
Channel Indicator Input.
(see Note 3)
CICSEL3 Reg Bit 6 = '1',
GPIS2 Reg Bits 28:29 = '01'
GP20
AC11
GPIO_20
IO
5V
General Purpose
Input/Output - Bit 20
GPOS Reg Bits 40:41 = '00'
INT23
I 5V
PowerPC
External Interrupt
#5 Input
GPIS1 Reg Bits 40:41 = '01'
DV2_HSYNC
IO
5V
Reserved
GPOS Reg Bits 40:41 = '10',
GPIS2 Reg Bits 40:41 = '01'
SSP_CLK
I 5V
Synchronous Serial Port for
Modem - Baud rate clock
GPIS3 Reg Bits 40:41 = '01'
DA_BIT_CLK
I 5V
I
2
S Digital Audio 64fs clock
input. Signal routed through
to GP13 (not bonded out)
CICSEL3 Reg Bit 6 = '1',
GPIS2 Reg Bits 26:27 = '01'
GP29
AE04
GPIO_29
IO
5V
General Purpose
Input/Output - Bit 29
GPOS Reg Bits 58:59 = '00'
XPT_PWM_OUTPUT
O 5V
System VCXO Pulse-Width
modulated Error Signal.
(See Note 6)
GPOS Reg Bits 58:59 = '10'
Pin
Name
Pin
No.
Function
Pin
Type
Description
Multiplex Configuration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL10311DTV-SOC | Digital Television DVB-T-On-a-Chip Processor |
| ZL10312QCF | Satellite Demodulator |
| ZL10312QCG | Satellite Demodulator |
| ZL10312QCG1 | Satellite Demodulator |
| ZL10312UBH | Satellite Demodulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL10310GAC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10311 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10311/GAC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10311DTV-SOC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10311GAC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
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