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參數(shù)資料
| 型號(hào)： | ZL10310 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Power Quality Recorder; Bandwidth Max:60Hz; Kit Contents:CTs, Voltage Leads, Ground Probes and Leads, PC Software and Download Cable; Voltage Rating:600V RoHS Compliant: NA |
| 中文描述： | 數(shù)字電視的DVB - T -上一芯片處理器 |
| 文件頁數(shù)： | 24/40頁 |
| 文件大?。?/td> | 670K |
| 代理商： | ZL10310 |
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ZL10310/ZL10311
Data Sheet
24
Zarlink Semiconductor Inc.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Multiplex setup with PORTMUX Register Bit [7] = ‘0’
Multiplex setup with PORTMUX Register Bit [7] = ‘1’
Multiplex setup with CIC Control Register Bit 3 = '1', & Bit 30 or Bit 31 = '0'
Multiplex setup with CIC Control Register Bit 3 = '1', & Bit 30 or Bit 31 = '1'
Multiplex setup with CIC Control Register Bit 3 = '0'
Multiplex setup with CIC Control Register Bit 3 = '1'
6.7 Peripheral Port
The Peripheral Port is provided with 10 pins that can be configured as general purpose I/O bits, or can provide
several alternative interfaces. The bit I/Os are provided by the GPIS (input) and GPOS (output) registers, along with
the PORTMUX and CIC Control Register bits, and only the bits listed below should be used.
There are multiplexed functions on these pins, and included is information on how to access these multiplexed
signals. The multiplexed functions include access to GPIO signals, DMA control signals, Infrared Port, Serial
Communications port, S/PDIF Audio bitstream output and some ancillary Common Interface Video control signals.
nEDMAC3_ACK
B06
nEDMAC3_ACK
O
External DMA Port 3 Acknowledge Output
for an IDE controller. Active Low.
nIDE_DMA_ACK
O
IDE Acknowledge Output. Active Low.
nEDMAC3_REQ
A06
nEDMAC3_REQ
I
External DMA Port 3 Request Input from an
IDE Controller. Active Low.
nIDE_DMA_REQ
I
IDE DMA Request Input. Active High.
nIDE_OE
AD16
nIDE_OE
O
IDE Output Enable signal for a bus
transceiver in the IDE data path. Active Low.
INT2
E24
INT2
I
PowerPC
External Interrupt #2 Input.
Connect to VDD_IO or ground if not
required.
Pin
Name
Pin
No.
Function
Pin
Type
Description
Multiplex Configuration
PP[0]
C12
GPIO_22
IO
General Purpose
Input/Output - Bit 22
PORTMUX Reg. Bit 8 = '0',
GPOS Reg Bits 44:45 = '00'
INT9
I
PowerPC
External Interrupt
#9 Input
PORTMUX Reg Bit 8 = '0',
GPIS3 Reg Bits 44:45 = '01'
EDMAC2_ACK
O
DMA Channel 2 External
Acknowledge Output
PORTMUX Reg Bit 8 = '1',
CIC Control Reg bits 26:27 = '10'
EBM_HOLDACK
IO
External Bus Master
(master/slave bus arbitration
controls) -
Hold Acknowledge flag
PORTMUX Reg Bit 8 = '1',
CIC Control Reg bits 26:27 = '11'
Pin Name
Pin
No.
Function
Pin
Type
Description
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL10310DTV-SOC | Digital Television DVB-T-On-a-Chip Processor |
| ZL10311DTV-SOC | Digital Television DVB-T-On-a-Chip Processor |
| ZL10312QCF | Satellite Demodulator |
| ZL10312QCG | Satellite Demodulator |
| ZL10312QCG1 | Satellite Demodulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL10310/GAC | 制造商:Microsemi Corporation 功能描述: |
| ZL10310DTV-SOC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10310GAC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10311 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10311/GAC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
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