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參數(shù)資料
| 型號： | ZL10310 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Power Quality Recorder; Bandwidth Max:60Hz; Kit Contents:CTs, Voltage Leads, Ground Probes and Leads, PC Software and Download Cable; Voltage Rating:600V RoHS Compliant: NA |
| 中文描述： | 數(shù)字電視的DVB - T -上一芯片處理器 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大?。?/td> | 670K |
| 代理商： | ZL10310 |
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ZL10310/ZL10311
Data Sheet
20
Zarlink Semiconductor Inc.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Multiplex setup with PORTMUX Register Bits [11:10] = ‘00’
Multiplex setup with PORTMUX Register Bits [11:10] = ‘10’
Multiplex setup with PORTMUX Register Bits [11:10] = ‘11’
Multiplex setup with PORTMUX Register Bits [11:10] = '01' & CICSEL3 Register Bit 2 = '0'. Also if BI_DATA[7] = '0' at Reset.
Multiplex setup with PORTMUX Register Bits [11:10] = '01' & CICSEL3 Register Bit 2 = '1'. Also if BI_DATA[7] = '1' at Reset.
Data Inputs MID [0:7] should be connected to GND or Vdd if NOT required.
MID[0]
Y02
CII_MDATA[0]
(MSB)
I
Common Interface Input - Bit 0 (MSB)
1, 6
BI_DATA[0] (MSB)
I
Auxiliary External Bus - Data Bit 0 (MSB)
(PCMCIA Data 15)
2, 6
MID[1]
Y01
CII_MDATA[1]
I
Common Interface Input - Bit 1
1, 6
BI_DATA[1]
I
Auxiliary External Bus - Data Bit 1
(PCMCIA Data 14)
2, 6
MID[2]
T04
CII_MDATA[2]
I
Common Interface Input - Bit 2
1, 6
BI_DATA[2]
I
Auxiliary External Bus - Data Bit 2
(PCMCIA Data 13)
2, 6
MID[3]
U03
CII_MDATA[3]
I
Common Interface Input - Bit 3
1, 6
BI_DATA[3]
I
Auxiliary External Bus - Data Bit 3
(PCMCIA Data 12)
2, 6
MID[4]
V01
CII_MDATA[4]
I
Common Interface Input - Bit 4
1, 6
BI_DATA[4]
I
Auxiliary External Bus - Data Bit 4
(PCMCIA Data 11)
2, 6
MID[5]
V02
CII_MDATA[5]
I
Common Interface Input - Bit 5
1, 6
BI_DATA[5]
I
Auxiliary External Bus - Data Bit 5
(PCMCIA Data 10)
2, 6
MID[6]
U01
CII_MDATA[6]
I
Common Interface Input - Bit 6
1, 6
BI_DATA[6]
I
Auxiliary External Bus - Data Bit 6
(PCMCIA Data 9)
2, 6
MID[7]
T03
CII_MDATA[7] (LSB)
I
Common Interface Input - Bit 7 (LSB)
1, 6
BI_DATA[7] (LSB)
I
Auxiliary External Bus - Data Bit 7 (LSB)
(PCMCIA Data 8)
2, 6
MISTRT
U02
CII_MSTRT
I
Common Interface Input - Packet Start Indicator.
Identifies the first byte in a transport packet of
188 bytes.
MICLK
W02
CII_MCLK
I
Common Interface Input - Bitstream Clock.
MIVAL
AA01
CII_MVAL
I
Common Interface Input - Data Valid Indicator.
Data Valid for the Current Clock Cycle for
Transmission.
Pin
Name
Pin
No.
Function
Pin
Type
Description
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL10310DTV-SOC | Digital Television DVB-T-On-a-Chip Processor |
| ZL10311DTV-SOC | Digital Television DVB-T-On-a-Chip Processor |
| ZL10312QCF | Satellite Demodulator |
| ZL10312QCG | Satellite Demodulator |
| ZL10312QCG1 | Satellite Demodulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL10310/GAC | 制造商:Microsemi Corporation 功能描述: |
| ZL10310DTV-SOC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10310GAC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10311 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10311/GAC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
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