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參數(shù)資料
| 型號(hào)： | ZL10310 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Power Quality Recorder; Bandwidth Max:60Hz; Kit Contents:CTs, Voltage Leads, Ground Probes and Leads, PC Software and Download Cable; Voltage Rating:600V RoHS Compliant: NA |
| 中文描述： | 數(shù)字電視的DVB - T -上一芯片處理器 |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 670K |
| 代理商： | ZL10310 |
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Data Sheet
ZL10310/ZL10311
17
Zarlink Semiconductor Inc.
Note 1:
SD0_CLK / SD1_CLK output is 50ohm impedance with 130ma/ns slew rate
6.5 Bit Stream Interfaces
The ZL10310 and ZL10311 devices have a fully DVB-compatible byte-wide Common Interface, which is a bitstream
data Input/Output bus. There are multiplexed functions on these pins, and included is information on how to access
these multiplexed signals. The multiplexed functions include access to Address/Data Bits of the Auxiliary External
Bus (configured on this interface to access PCMCIA (PC) Cards), RISC Trace debug ports, Simplified GPIO Bus 1
and Smart Card Interface 1.
The Data pins for Output (MOD[0:7]) and Input (MID[0:7]) are configured as “Big Endian”. This means that bit [0] is
the Most Significant Bit (MSB) for the Common Interface and Auxiliary Bus signals.
SD0_DATA[01]
AD19
B
SDRAM0 Bus - Data Bit 1
SD0_DATA[02]
AD20
B
SDRAM0 Bus - Data Bit 2
SD0_DATA[03]
AF20
B
SDRAM0 Bus - Data Bit 3
SD0_DATA[04]
AD21
B
SDRAM0 Bus - Data Bit 4
SD0_DATA[05]
AE21
B
SDRAM0 Bus - Data Bit 5
SD0_DATA[06]
AE22
B
SDRAM0 Bus - Data Bit 6
SD0_DATA[07]
AF23
B
SDRAM0 Bus - Data Bit 7
SD0_DATA[08]
AD23
B
SDRAM0 Bus - Data Bit 8
SD0_DATA[09]
AD22
B
SDRAM0 Bus - Data Bit 9
SD0_DATA[10]
AF22
B
SDRAM0 Bus - Data Bit 10
SD0_DATA[11]
AF21
B
SDRAM0 Bus - Data Bit 11
SD0_DATA[12]
AC21
B
SDRAM0 Bus - Data Bit 12
SD0_DATA[13]
AE20
B
SDRAM0 Bus - Data Bit 13
SD0_DATA[14]
AE19
B
SDRAM0 Bus - Data Bit 14
SD0_DATA[15]
AF18
B
SDRAM0 Bus - Data Bit 15 (LSB)
SD0_DQMH
AE24
O
SDRAM0 Bus - Data Bus Mask High. Active High
SD0_DQML
AD18
O
SDRAM0 Bus - Data Bus Mask Low. Active High
nSD0_RAS
AD25
O
SDRAM0 Bus - Row Address Strobe. Active Low.
Also known as SDRAM0 Command Bit 2 (MSB).
nSD0_CAS
AF24
O
SDRAM0 Bus - Column Address Strobe. Active Low.
Also known as SDRAM0 Command Bit 1.
nSD0_WE
AE23
O
SDRAM0 Bus - Write Enable. Active Low.
Also known as SDRAM0 Command Bit 0 (LSB).
SD0_CLK
AE26
O
SDRAM0 Bus - Clock Output
1
nSD0_CS0
AD26
O
SDRAM0 Bus - Chip Select 0. Active Low
Pin Name
Pin No.
Pin
Type
Description
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL10310DTV-SOC | Digital Television DVB-T-On-a-Chip Processor |
| ZL10311DTV-SOC | Digital Television DVB-T-On-a-Chip Processor |
| ZL10312QCF | Satellite Demodulator |
| ZL10312QCG | Satellite Demodulator |
| ZL10312QCG1 | Satellite Demodulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL10310/GAC | 制造商:Microsemi Corporation 功能描述: |
| ZL10310DTV-SOC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10310GAC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10311 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
| ZL10311/GAC | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Television DVB-T-On-a-Chip Processor |
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