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參數(shù)資料
| 型號(hào)： | Z86L9208VSC |
| 廠商： | ZILOG INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | IR MICROCONTROLLER |
| 中文描述： | 8-BIT, 8 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 57/71頁 |
| 文件大?。?/td> | 364K |
| 代理商： | Z86L9208VSC |
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Z86C72/C92/L72/L92
IR Microcontroller
Zilog
DS97LVO0900
P R E L I M I N A R Y
6-57
1
Watch-Dog Timer Mode Register (WDTMR).
The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT must initially be en-
abled by executing the WDT instruction and refreshed on
subsequent executions of the WDT instruction. The WDT
circuit is driven by an on-board RC oscillator or external
oscillator from the XTAL1 pin. The WDT instruction affects
the Zero (Z), Sign (S), and Overflow (V) flags.
The POR clock source is selected with bit 4 of the WDT
register. Bit 0 and 1 control a tap circuit that determines the
time-out period. Bit 2 determines whether the WDT is ac-
tive during HALT and Bit 3 determines WDT activity during
STOP. Bits 5 through 7 are reserved (Figure 42). This reg-
ister is accessible only during the first 64 processor cycles
(128 XTAL clocks) from the execution of the first instruc-
tion after Power-On-Reset, Watch-Dog Reset, or a Stop-
Mode Recovery (Figure 38). After this point, the register
cannot be modified by any means, intentional or other-
wise. The WDTMR cannot be read and is located in Bank
F of the Expanded Register Group at address location
0FH. It is organized as follows:
Figure 42. Watch-Dog Timer Mode Register
(Write Only)
D7
D6
D5
D4
D3
D2
D1
D0
WDTMR (0F) 0F
WDT TAP INT RC OSC External Clock
00 5 ms 256 TpC
01*
10 20 ms 1024 TpC
11 80 ms 4096 TpC
WDT During HALT
0 OFF
1 ON
*
WDT During STOP
0 OFF
1 ON
*
XTAL1/INT RC Select for WDT
0 On-Chip RC
1 XTAL
Reserved (Must be 0)
* Default Setting After Reset
*
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