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參數(shù)資料
| 型號(hào)： | Z86L9208VSC |
| 廠商： | ZILOG INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | IR MICROCONTROLLER |
| 中文描述： | 8-BIT, 8 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 53/71頁(yè) |
| 文件大?。?/td> | 364K |
| 代理商： | Z86L9208VSC |
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Z86C72/C92/L72/L92
IR Microcontroller
Zilog
DS97LVO0900
P R E L I M I N A R Y
6-53
1
Comparator Output Port 3 (D0).
Bit 0 controls the com-
parator used in Port 3. A 1 in this location brings the com-
parator outputs to P34 and P37, and a 0 releases the Port
to its standard I/O configuration.
Stop-Mode Recovery Register (SMR).
This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 38). All bits are write only ex-
cept bit 7, which is read only. Bit 7 is a flag bit that is hard-
ware set on the condition of STOP recovery and reset by
a power-on cycle. Bit 6 controls whether a low level or a
high level is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits D2, D3, and D4, of
the SMR register, specify the source of the Stop-Mode Re-
covery signal. Bit D0 determines if SCLK/TCLK are divided
by 16 or not. The SMR is located in Bank F of the Expand-
ed Register Group at address 0BH.
Figure 38. Stop-Mode Recovery Register
D7
D6
D5
D4
D3
D2
D1
D0
SMR (0F) 0B
SCLK/TCLK Divide-by-16
0 OFF
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000
001
010
011
100
101
110
111
Stop Delay
0 OFF
1 ON
*
Stop Recovery Level
0 Low
1 High
Stop Flag
0 POR
1 Stop Recovery**
* Default Setting After Reset
** Default Setting After Reset and Stop-Mode Recovery
**
*
*
*
POR Only
Reserved
P31
P32
P33
P27
P2 NOR 0-3
P2 NOR 0-7
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