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參數(shù)資料
| 型號： | Z80L182 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CAP .0001UF 50V POLYPROPYLENE |
| 中文描述： | ZiLOG的智能外設控制器（郵編⑩） |
| 文件頁數(shù)： | 74/109頁 |
| 文件大?。?/td> | 738K |
| 代理商： | Z80L182 |
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3-74
Z80182/Z8L182
Z
ILOG
I
NTELLIGENT
P
ERIPHERAL
P R E L I M I N A R Y
Zilog
DS971820600
16550 MIMIC REGISTERS
(Continued)
Modem Status Register
Bit 7 Data Carrier Detect
This bit must be written by the Z180 MPU.
Bit 6 Ring Indicator
This bit must be written by the Z180 MPU.
Bit 5 Data Set Ready
This bit must be written by the Z180 MPU.
Bit 4 Clear to Send
This bit must be written by the Z180
MPU.
Bit 3 Delta Data Carrier Detect
This bit is set to 1 whenever the Data Carrier Detect bit
changes state. This bit is reset when the PC/XT/AT reads
the Modem Status Register.
Bit 2 Trailing Edge Ring Indicator
This bit is set to 1 on the falling edge of the Ring Indicator
bit. This bit is reset when the PC/XT/AT reads the Modem
Status Register.
Bit 1 Delta Data Set Ready
This bit is set to 1 whenever the Data Set Ready bit
changes state. This bit is reset when the PC/XT/AT reads
the Modem Status Register.
Bit 0 Delta Clear To Send
This bit is set to 1 whenever the Clear To Send bit changes
state. This bit is reset when the PC/XT/AT reads the Modem
Status Register.
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Divisor Latch (LS)
Figure 79. Scratch Register
(PC Read/Write, Address 07H)
(Z180 MPU Read Only, Address xxF7H)
Scratch Register
Bits 7-0 Scratch Register
This register is used by the PC/XT/AT programmer for
temporary data storage. The Z180 MPU is able to read this
register. If the PC/XT/AT writes to this register, no interrupt
to the Z180 MPU is generated.
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Divisor Latch (MS)
Figure 80. Divisor Latch (LS)
(PC Read/Write, Address 00H and DLAB=1)
(Z180 MPU Read Only, Address xxF8H)
Divisor Latch (LS)
Bit 7-0 Divisor Latch Most Significant Byte (MS)
This register contains the Low order byte of the Baud rate
divisor. Writing to this register with the PC/XT/AT will
generate an interrupt to the Z180 MPU. It can then read the
Baud rate divisor and set up the application.
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Scratch Register
Figure 81. Divisor Latch (MS)
(PC Read/Write, Address 01H and DLAB=1)
(Z180 MPU Read Only, Address xxF9H)
Divisor Latch (MS)
Bit 7-0 Divisor Latch Most Significant Byte (MS)
This register contains the High order byte of the Baud rate
divisor. Writing to this register with the PC/XT/AT will
generate an interrupt to the Z180 MPU. It can then read the
Baud rate divisor and set up the application.
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