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參數(shù)資料
| 型號： | Z80L182 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | CAP .0001UF 50V POLYPROPYLENE |
| 中文描述： | ZiLOG的智能外設(shè)控制器（郵編⑩） |
| 文件頁數(shù)： | 26/109頁 |
| 文件大?。?/td> | 738K |
| 代理商： | Z80L182 |
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3-26
Z80182/Z8L182
Z
ILOG
I
NTELLIGENT
P
ERIPHERAL
P R E L I M I N A R Y
Zilog
DS971820600
Z80182 MIMIC DOUBLE BUFFERING FOR THE TRANSMITTER
The Z80182 Rev DA implements double buffering for the
transmitter in 16450 mode and sets the TEMT bit in the LSR
Register automatically.
When this feature is enabled and character delay emulation
is being used (see Figure 9):
1.
The PC THRE bit in the LSR Register is set when the
THR Register is empty;
2.
PC Host writes to the 16450 THR Register;
3.
Whenever the Z80182 TSR buffer is empty and one
character delay timer is in a timed-out state, the byte
from the THR Register is transferred to the TSR buffer;
the timer is in timed-out state after FIFO Reset or after
Host TEMT is set. This allows a dual write to THR when
Host TEMT is set.
4.
Restart character delay timer (timer reloads and counts
down) with byte transfer from THR Register to the TSR
buffer;
5.
Whenever the TSR buffer is full, the TEMT bit in MPU
LSR Register is reset with no delay;
6.
MPU reads TSR buffer;
7.
TEMT bit in LSR Register for MPU is set with no delay
whenever the TSR buffer is empty;
8.
When the TSR buffer is read by MPU and THR Register
is empty and one character delay timer reaches zero,
the TEMT bit in the LSR Register for Host is set from 0
to 1.
The PC THRE bit in the LSR Register is reset whenever the
THR Register is full and set whenever THR Register is
empty.
MPU IREQ and DMA Request for the transmit data is
trigger whenever TSR buffer is full and cleared whenever
TSR buffer is empty.
If character delay emulation is not used the TEMT bit in the
LSR Register is set whenever both the THR Register and
the TSR buffer are both empty. The Host TEMT bit is clear
if there is data in either the TSR buffer of THR Register.
16450
THR
Register
Host Write
Empty/Full
Host & MPU THRE = 1 0
Byte Transfer if:
- THRE=0;
- TSR = 1;
- Character delay timer is timed out.
Note: Timer reloads and counts down
whenever data is transferred from THR to TSR.
THR to TSR
delay
transfer
TSR
Transmit
Shift Reg.
Emulation
Empty/Full
(MPU TEMT) TSRE = 1 0
Host TEMT = 1 if - THRE = 1
- TSRE = 1
- Emulation delay timer is timed out
Note: MPU sees TSR bit in the LSR Register as TEMT bit
Added TSR Buffer for the
transmit data
Figure 9. TEMT Emulation Logic Implementation
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