參數(shù)資料
型號： XRT91L32
廠商： Exar Corporation
英文描述： STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
中文描述： STS-12/STM-4或STS-3/STM-1的SONET / SDH收發(fā)器
文件頁數(shù)： 4/37頁
文件大?。?/td> 417K
代理商： XRT91L32
XRT91L32
REV. 1.0.2
xr
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
APPLICATIONS...........................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
XRT91L32...................................................................................................................................... 1
FEATURES
......................................................................................................................................................2
F
IGURE
2. 100 QFP P
IN
O
UT
OF
THE
XRT91L32 (T
OP
V
IEW
).......................................................................................................... 3
ORDERING INFORMATION.....................................................................................................................3
T
ABLE
OF
C
ONTENTS
............................................................................................................
I
PIN DESCRIPTIONS ..........................................................................................................4
.....................................................................................................................................................................4
H
ARDWARE
C
ONTROL
....................................................................................................................................4
T
RANSMITTER
S
ECTION
..................................................................................................................................6
R
ECEIVER
S
ECTION
........................................................................................................................................8
P
OWER
AND
G
ROUND
....................................................................................................................................9
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................11
1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 11
1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 11
T
ABLE
1: CMU R
EFERENCE
F
REQUENCY
O
PTIONS
(D
IFFERENTIAL
OR
S
INGLE
-E
NDED
) ................................................................... 11
1.3 DATA LATENCY ............................................................................................................................................. 11
T
ABLE
2: D
ATA
INGRESS
TO
DATA
EGRESS
LATENCY
....................................................................................................................... 11
2.0 RECEIVE SECTION .............................................................................................................................12
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 12
F
IGURE
3. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
B
LOCK
..................................................................................................................... 12
2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 13
F
IGURE
4. R
ECEIVE
H
IGH
-S
PEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
D
IAGRAM
.......................................................................................... 13
T
ABLE
3: R
ECEIVE
H
IGH
-
SPEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
) ............................................................. 13
T
ABLE
4: R
ECEIVE
H
IGH
-S
PEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
)............................................................... 13
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 14
T
ABLE
5: C
LOCK
D
ATA
R
ECOVERY
UNIT
REFERENCE
CLOCK
SETTINGS
............................................................................................ 14
T
ABLE
6: C
LOCK
AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
.......................................................................................................... 15
2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................ 15
F
IGURE
5. I
NTERNAL
C
LOCK
AND
D
ATA
R
ECOVERY
B
YPASS
............................................................................................................ 15
2.4 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16
F
IGURE
6. E
XTERNAL
L
OOP
F
ILTERS
.............................................................................................................................................. 16
2.5 LOSS OF SIGNAL .......................................................................................................................................... 16
F
IGURE
7. LOS D
ECLARATION
CIRCUIT
........................................................................................................................................... 16
2.6 SONET FRAME BOUNDARY DETECTION AND BYTE ALIGNMENT RECOVERY .................................... 17
2.7 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 17
F
IGURE
8. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
SIPO ........................................................................................................................... 17
2.8 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 18
F
IGURE
9. R
ECEIVE
P
ARALLEL
O
UTPUT
I
NTERFACE
B
LOCK
............................................................................................................. 18
2.9 DISABLE PARALLEL RECEIVE DATA OUTPUT UPON LOS ..................................................................... 18
2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 19
F
IGURE
10. R
ECEIVE
P
ARALLEL
O
UTPUT
T
IMING
............................................................................................................................ 19
T
ABLE
7: R
ECEIVE
P
ARALLEL
D
ATA
O
UTPUT
T
IMING
(STS-12/STM-4 O
PERATION
)......................................................................... 19
T
ABLE
8: R
ECEIVE
P
ARALLEL
D
ATA
O
UTPUT
T
IMING
(STS-3/STM-1 O
PERATION
)........................................................................... 19
T
ABLE
9: PECL
AND
TTL R
ECEIVE
O
UTPUTS
T
IMING
S
PECIFICATION
.............................................................................................. 20
3.0 TRANSMIT SECTION ..........................................................................................................................21
3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 21
F
IGURE
11. T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
............................................................................................................. 21
3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 22
F
IGURE
12. T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
.............................................................................................................................. 22
T
ABLE
10: T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
)......................................................................... 22
T
ABLE
11: T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
)........................................................................... 22
3.3 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 23
F
IGURE
13. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
PISO ......................................................................................................................... 23
3.4 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 23
T
ABLE
12: C
LOCK
M
ULTIPLIER
U
NIT
P
ERFORMANCE
....................................................................................................................... 23
3.5 LOOP TIMING AND CLOCK CONTROL ........................................................................................................ 24
T
ABLE
13: L
OOP
T
IMING
AND
C
LOCK
R
ECOVERY
CONFIGURATIONS
................................................................................................. 24
相關PDF資料
PDF描述
XRT91L32IQ-F STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80_0507 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
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