參數(shù)資料
型號： XRT86VX38IB329-F
廠商： Exar Corporation
文件頁數(shù)： 18/61頁
文件大?。?/td> 0K
描述： IC TI/E1/J1 FRAMER/LIU 329FPBGA
標(biāo)準(zhǔn)包裝： 90
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 329-FBGA
供應(yīng)商設(shè)備封裝： 329-FPBGA（17x17）
包裝： 散裝
其它名稱： 1016-1439
XRT86VX38
22
REV. 1.0.3
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RxSig0
RxSig1
RxSig2
RxSig3
RxSig4
RxSig5
RxSig6
RxSig7
A7
B12
C16
D18
U18
W14
V12
U9
O8
Receive Serial Signaling Output (RxSIGn):
The exact function of these pins depends on whether or
not the receive framer enables the receive fractional/sig-
naling interface, as described below:
If receive fractional/signaling interface is disabled :
-No function
If receive fractional/signaling interface is enabled -
RxSIGn:
These pins can be used to output robbed-bit signaling
data within an inbound DS1 frame or to output Channel
Associated Signaling (CAS) data within an inbound E1
frame, as described below.
T1 Mode: Signaling data (A,B,C,D) of each channel will
be output on bit 4,5,6,7 of each time slot on the RxSIG pin
if 16-code signaling is used. If 4-code signaling is
selected, signaling data (A,B) of each channel will be out-
put on bit 4, 5 of each time slot on the RxSIG pin. If 2-
code signaling is selected, signaling data (A) of each
channel will be output on bit 4 of each time slot on the
RxSIG pin.
E1 Mode: Signaling data in E1 mode will be output on the
RxSIGn pins on a time-slot-basis as in T1 mode, or it can
be output on time slot 16 only via the RxSIGn output pins.
In the latter case, signaling data (A,B,C,D) of channel 1
and channel 17 will be output on the RxSIGn pin during
time slot 16 of frame 1, signaling data (A,B,C,D) of chan-
nel 2 and channel 18 will be output on the RxSIGn pin
during time slot 16 of frame 2...etc. The CAS multiframe
Alignments bits (0000 bits) and the extra bits/alarm bit
(xyxx) will be output on the RxSIGn pin during time slot 16
of frame 0.
NOTE:
Receive Fractional/signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from register 0xn122 to ‘1’.
RxSCLK0
RxSCLK1
RxSCLK2
RxSCLK3
RxSCLK4
RxSCLK5
RxSCLK6
RxSCLK7
C11
E14
A18
F17
W18
T14
U11
U8
B10
D12
A15
F12
T15
T11
P9
M7
O8
Receive Recovered Line Clock Output (RxSCLKn):
The exact function of these pins depends on whether or
not the receive framer enables the receive fractional/sig-
naling interface, as described below:
If receive fractional/signaling interface is disabled -
-No function
If receive fractional/signaling interface is enabled -
Receive Recovered Line Clock Output (RxSCLKn):
These pins output the recovered T1/E1 line clock
(1.544MHz in T1 mode and 2.048MHz in E1 mode) for
each channel.
NOTE:
Receive Fractional/Signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from register 0xn122 to ‘1’.
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
DESCRIPTION
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