參數(shù)資料
型號： XRT86VX38IB329-F
廠商： Exar Corporation
文件頁數(shù)： 13/61頁
文件大?。?/td> 0K
描述： IC TI/E1/J1 FRAMER/LIU 329FPBGA
標(biāo)準(zhǔn)包裝： 90
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 329-FBGA
供應(yīng)商設(shè)備封裝： 329-FPBGA（17x17）
包裝： 散裝
其它名稱： 1016-1439
XRT86VX38
17
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. 1.0.3
TxSIG0
TxSIG1
TxSIG2
TxSIG3
TxSIG4
TxSIG5
TxSIG6
TxSIG7
A10
B15
B18
G18
V16
W13
U10
U6
I/O
8
Transmit Time Slot Octet Identifier Output 0 (TxCHNn_0) /
Transmit Serial Signaling Input (TxSIGn):
The exact function of these pins depends on whether or not
the transmit framer enables the transmit fractional/signaling
interface, as described below:
If transmit fractional/signaling interface is disabled -
- No function
If transmit fractional/signaling interface is enabled -
TxSIGn:
These pins can be used to input robbed-bit signaling data to
be inserted within an outbound DS1 frame or to input Channel
Associated Signaling (CAS) data within an outbound E1
frame, as described below.
T1 Mode: Signaling data (A,B,C,D) of each channel must be
provided on bit 4,5,6,7 of each time slot on the TxSIG pin if 16-
code signaling is used. If 4-code signaling is selected, signal-
ing data (A,B) of each channel must be provided on bit 4, 5 of
each time slot on the TxSIG pin. If 2-code signaling is
selected, signaling data (A) of each channel must be provided
on bit 4 of each time slot on the TxSIG pin.
E1 Mode: Signaling data in E1 mode can be provided on the
TxSIGn pins on a time-slot-basis as in T1 mode, or it can be
provided on time slot 16 only via the TxSIGn input pins. In the
latter case, signaling data (A,B,C,D) of channel 1 and channel
17 must be inserted on the TxSIGn pin during time slot 16 of
frame 1, signaling data (A,B,C,D) of channel 2 and channel 18
must be inserted on the TxSIGn pin during time slot 16 of
frame 2...etc. The CAS multiframe Alignments bits (0000 bits)
and the extra bits/alarm bit (xyxx) must be inserted on the
TxSIGn pin during time slot 16 of frame 0.
NOTE:
Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
NOTE:
These 8 pins are internally pulled “Low” for each
channel.
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE(MA)
DESCRIPTION
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