參數(shù)資料
型號(hào)： XRT86VX38IB329-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 16/61頁(yè)
文件大?。?/td> 0K
描述： IC TI/E1/J1 FRAMER/LIU 329FPBGA
標(biāo)準(zhǔn)包裝： 90
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 329-FBGA
供應(yīng)商設(shè)備封裝： 329-FPBGA（17x17）
包裝： 散裝
其它名稱： 1016-1439
XRT86VX38
20
REV. 1.0.3
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RxSERCLK0/
RxLINECLK0
RxSERCLK1/
RxLINECLK1
RxSERCLK2/
RxLINECLK2
RxSERCLK3/
RxLINECLK3
RxSERCLK4/
RxLINECLK4
RxSERCLK5/
RxLINECLK5
RxSERCLK6/
RxLINECLK6
RxSERCLK7/
RxLINECLK7
D9
A11
B16
F16
R17
T15
T12
U7
B8
A10
C13
D15
P14
T12
M10
R6
I/O
12
Receive Serial Clock Signal (RxSERCLKn) / Receive
Line Clock (RxLINECLKn):
The exact function of these pins depends on the mode of
operation selected, as described below.
In Base-Rate Mode (1.544MHz/2.048MHz) - RxSER-
CLKn:
These pins are used as the receive serial clock on the
system side interface which can be configured as either
input or output. The receive serial interface outputs data
on RxSERn on the rising edge of RxSERCLKn.
When RxSERCLKn is configured as Input:
These pins will be inputs if the slip buffer on the Receive
path is enabled. System side equipment must provide a
1.544MHz clock rate to this input pin for T1 mode of oper-
ation, and 2.048MHz clock rate in E1 mode.
When RxSERCLKn is configured as Output:
These pins will be outputs if slip buffer is bypassed. The
receive framer will output a 1.544MHz clock rate in T1
mode of operation, and a 2.048MHz clock rate in E1
mode.
DS1/E1 High-Speed Backplane Modes* - (RxSERCLK
as INPUT ONLY)
In this mode, this pin must be used as the high-speed
input clock for the backplane interface to output high-
speed or multiplexed data on the RxSERn pin. The fre-
quency of RxSERCLK is presented in the table below.
NOTES:
1.
*High-speed backplane modes include (For T1/
E1)
2.048MVIP,
4.096MHz,
8.192MHz,
16.384MHz
HMVIP,
H.100,
Bit-multiplexed
modes, and (For T1 only) 12.352MHz Bit-
multiplexed mode.
2.
For DS1 high-speed modes, the DS-0 data is
mapped into an E1 frame by ignoring every
fourth time slot (don’t care).
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME
329 PKG
BALL#
256 PKG
BALL #
TYPE
OUTPUT
DRIVE (MA)
DESCRIPTION
OPERATION MODE
FREQUENCY OF
RXSERCLK(MHZ)
2.048MVIP non-multiplexed
2.048
4.096MHz non-multiplexed
4.096
8.192MHz non-multiplexed
8.192
12.352MHz Bit-multiplexed
(DS1 ONLY)
12.352
16.384MHz Bit-multiplexed
16.384
16.384 HMVIP Byte-multiplexed
16.384
16.384 H.100 Byte-multiplexed
16.384
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