參數(shù)資料
型號： XRT86VL3X_07
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 90/153頁
文件大?。?/td> 1316K
代理商： XRT86VL3X_07
XRT86VL3X
83
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.2
T1 Receive Multiplexed Mode
The interface consists of the following pins:
Data Output (RxSer_n)
Receive Serial Clock Input signal (RxSerClk_n)
Receive Single-frame Synchronization Input signal (RxSync_n)
The Receive Back-plane Interface is pumping out data through RxSer_0 or RxSer_4 pins at 12.352Mbit/s or
16.384Mbit/s. It multiplexes payload and signaling data of every four channels into one data stream. Payload
and signaling data of Channel 0-3 are multiplexed onto the Receive Serial Data pin of Channel 0. Payload and
signaling data of Channel 4-7 are multiplexed onto the Receive Serial Data pin of Channel 4.
Free-running clocks of 12.352MHz or 16.384MHz are supplied to the Receive Serial Clock pin of Channel 0
and Channel 4 of the framer. The Receive High-speed Back-plane Interface of the farmer provides data at
rising edge of this Receive Serial Clock. The local Terminal Equipment then latches incoming serial data at
falling edge of the clock. Figure 89 shows the interface of the Recieve Payload Data Output Interface Block to
the Terminal Equipment.
The multiplexed data output on RxSER_0 or RxSER_4 are very similar to the Multiplexed data input on
TxSER_0 or TxSER_4 except when the receive framer is running at 12.352MHz or 16.384MHz Bit-Multiplexed
mode. When the receive framer is running at 12MHz or 16MHz Bit-Multiplexed mode, the multiplexed data on
RxSER_0 or RxSER_4 are return-to-zero data when the receive framer is processing the first four bits of each
time slot data of each channel, as shown in Figure 90 and Figure 91. Figure 92 shows the timing signal when
the receive framer is running at HMVIP or H.100 16.384 MHz mode.
F
IGURE
88. T
IMING
SIGNALS
WHEN
THE
TRANSMIT
FRAMER
IS
RUNNING
AT
HMVIP / H.100 16.384MH
Z
M
ODE
TxInClk (16.384MHz)
TxInClk (INV)
TxSer
1
2
1
2
5
2
5
2
1
0
1
0
2
0
2
0
X
y
: X is the bit number and y is the channel number
0
0
3
0
4
0
3
0
4
0
5
0
5
0
6
0
6
0
7
3
7
3
8
3
8
3
F
0
F
0
F
0
F
0
F
0
F
0
F
0
F
0
56 cycles
5
3
5
3
6
3
6
3
7
3
7
3
8
3
8
3
0
0
A
2
A
2
0 0 0 0
0
A
0
0
A
0
B
0
B
0
C
3
C
3
D
3
D
3
1
1
1
1
1 1 1 1
56 cycles
A
3
A
3
B
3
B
3
C
3
C
3
D
3
D
3
TxSig
TxSync(input)
HMVIP, negative sync
TxSync(input)
HMVIP, positive sync
Start of Frame
TxSync(input)
H.100, negative sync
TxSync(input)
H.100, positive sync
Delayer H.100
TxSync(input)
H.100, negative sync
TxSync(input)
H.100, positive sync
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