XRT86VL34
A
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
LIST OF TABLES
Table 1:: Register Summary ..............................................................................................................................................4
Table 2:: Clock Select Register(CSR) Hex Address: 0xn100 ........10
Table 3:: Line Interface Control Register (LICR) Hex Address: 0xn101 ...............12
Table 4:: Framing Select Register (FSR) Hex Address: 0xn107 ....................14
Table 5:: Alarm Generation Register (AGR) Hex Address: 0xn108 ......................16
Table 6:: yellow alarm duration and format when one second rule is not enforced .........................................................17
Table 7:: yellow alarm format when one second rule is enforced ....................................................................................18
Table 8:: Synchronization MUX Register (SMR) Hex Address: 0xn109 ...................20
Table 9:: Transmit Signaling and Data Link Select Register (TSDLSR) Hex Address:0xn10A ....................23
Table 10:: Framing Control Register (FCR) Hex Address: 0xn10B ..................25
Table 11:: Receive Signaling & Data Link Select Register (RSDLSR) Hex Address: 0xn10C ....................26
Table 12:: Receive Signaling Change Register 0 (RSCR 0) Hex Address: 0xn10D ...........28
Table 13:: Receive Signaling Change Register 1(RSCR 1) Hex Address: 0xn10E .......28
Table 14:: Receive Signaling Change Register 2 (RSCR 2) Hex Address: 0xn10F .........28
Table 15:: Receive In Frame Register (RIFR) Hex Address: 0xn112 ...................29
Table 16:: Data Link Control Register (DLCR1) Hex Address: 0xn113 ....................29
Table 17:: Transmit Data Link Byte Count Register (TDLBCR1) Hex Address: 0xn114 ....................32
Table 18:: Receive Data Link Byte Count Register (RDLBCR1) Hex Address: 0xn115 ...................33
Table 19:: Slip Buffer Control Register (SBCR) Hex Address: 0xn116 ......................34
Table 20:: FIFO Latency Register (FFOLR) Hex Address: 0xn117 ................35
Table 21:: DMA 0 (Write) Configuration Register (D0WCR) Hex Address: 0xn118 ..................36
Table 22:: DMA 1 (Read) Configuration Register (D1RCR) Hex Address: 0xn119 ..................37
Table 23:: Interrupt Control Register (ICR) Hex Address: 0xn11A ......................38
Table 24:: LAPD Select Register (LAPDSR) Hex Address: 0xn11B .................38
Table 25:: Customer Installation Alarm Generation Register (CIAGR) Hex Address: 0xn11C ........................39
Table 26:: Performance Report Control Register (PRCR) Hex Address: 0xn11D .....................40
Table 27:: Gapped Clock Control Register (GCCR) Hex Address: 0xn11E ..................41
Table 28:: Transmit Interface Control Register (TICR) Hex Address:0xn120 .....................42
Table 29:: Transmit Interface Speed When Multiplexed Mode is Disabled (TxMUXEN = 0) ...........................................44
Table 30:: Transmit Interface Speed when Multiplexed Mode is Enabled (TxMUXEN = 1) ............................................45
Table 31:: PRBS Control & Status Register (PRBSCSR0) Hex Address: 0xn121 ...............46
Table 32:: Receive Interface Control Register (RICR) Hex Address: 0xn122 ..............48
Table 33:: Receive Interface Speed When Multiplexed Mode is Disabled (TxMUXEN = 0) ............................................50
Table 34:: Receive Interface Speed when Multiplexed Mode is Enabled (TxMUXEN = 1) .............................................51
Table 35:: PRBS Control & Status Register (PRBSCSR1) Hex Address: 0xn123 .....................52
Table 36:: Loopback Code Control Register (LCCR) Hex Address: 0xn124 ................54
Table 37:: Transmit Loopback Coder Register (TLCR) Hex Address: 0xn125 ..............56
Table 38:: Receive Loopback Activation Code Register (RLACR) Hex Address: 0xn126 .................56
Table 39:: Receive Loopback Deactivation Code Register (RLDCR) Hex Address: 0xn127 ...................56
Table 40:: Defect Detection Enable Register (DDER) Hex Address: 0xn129 ...............57
Table 41:: Transmit SPRM Control Register (TSPRMCR) Hex Address: 0xn142 .................57
Table 42:: Data Link Control Register (DLCR2) Hex Address: 0xn143 ...................58
Table 43:: Transmit Data Link Byte Count Register (TDLBCR2) Hex Address: 0xn144 ...................60
Table 44:: Receive Data Link Byte Count Register (RDLBCR2) Hex Address: 0xn145 ..................61
Table 45:: Data Link Control Register (DLCR3) Hex Address: 0xn153 ..................62
Table 46:: Transmit Data Link Byte Count Register (TDLBCR3) Hex Address: 0xn154 ...................64
Table 47:: Receive Data Link Byte Count Register (RDLBCR3) Hex Address: 0xn155 ..................65
Table 48:: Device ID Register (DEVID) Hex Address: 0xn1FE ............66
Table 49:: Revision ID Register (REVID) Hex Address: 0xn1FF ...........66
Table 50:: Transmit Channel Control Register 0-23 (TCCR 0-23) Hex Address: 0xn300 to 0xn317 .....................67
Table 51:: Transmit User Code Register 0-23 (TUCR 0-23) Hex Address: 0xn320 to 0xn337 ................69
Table 52:: Transmit Signaling Control Register 0-23 (TSCR 0-23) Hex Address: 0xn340 to 0xn357 .......................70
Table 53:: Receive Channel Control Register 0-23 (RCCR 0-23) Hex Address: 0xn360 to 0xn377 ...................72
Table 54:: Receive User Code Register 0-23 (RUCR 0-23) Hex Address: 0xn380 to 0xn397 ..............74
Table 55:: Receive Signaling Control Register 0-23 (RSCR 0-23) Hex Address: 0xn3A0 to 0xn3B7 ....................75
Table 56:: Receive Substitution Signaling Register 0-23 (RSSR 0-23) Hex Address: 0xn3C0 to 0xn3D7 ...................77
Table 57:: Receive Signaling Array Register 0 to 23 (RSAR 0-23) Hex Address: 0Xn500 to 0xn517 ...................78
Table 58:: LAPD Buffer 0 Control Register (LAPDBCR0) Hex Address: 0xn600 ....................................79