參數(shù)資料
型號: XRT86VL34_2
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 20/156頁
文件大?。?/td> 816K
代理商: XRT86VL34_2
XRT86VL34
15
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
3
FASTSYNC
R/W
0
Faster Sync Algorithm
This bit is used to specify one of the synchronization criteria that the
Receive T1 Framer block employs. If this “Faster Sync Algorithm” is
enabled, the Receive T1 Framer Block will declare synchronization
earlier. The table below specifies the number of consecutive frames
with correct F-bits that the T1 Receive framer must receive in order
to declare “SYNC” when FASTSYNC is enabled or disabled.
0 - Disables FASTSYNC feature.
1 - Enables FASTSYNC feature.
2-0
FSl[2:0]
R/W
000
T1 Framing Mode Select [2:0]
These three bits permit the user to select the exact T1 framing format
that the channel is to operate in.
Bit 2 is MSB and Bit 0 is LSB. The following table shows the five dif-
ferent framing formats that can be selected by configuring these
three bits accordingly.
N
OTE
:
Changing Framing formats 'on the fly' will cause the Receive
T1 Framer block to undergo a “Reframe” event.
T
ABLE
4: F
RAMING
S
ELECT
R
EGISTER
(FSR) H
EX
A
DDRESS
: 0
X
n107
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
Framing
FastSync
= 0
96
FastSync
= 1
48
ESF
SF
48
24
N
48
24
SLC
96
48
24
Framing
FS[2]
FS[1]
FS[0]
ESF
0
X
X
SF
1
0
1
N
1
1
0
T1DM
1
1
1
SLC
96
1
0
0
相關(guān)PDF資料
PDF描述
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB484 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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參數(shù)描述
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XRT86VL38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL38_07 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION