參數(shù)資料
型號(hào): XRT86VL34_2
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 102/156頁(yè)
文件大小: 816K
代理商: XRT86VL34_2
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XRT86VL34
97
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
83: F
RAMER
I
NTERRUPT
E
NABLE
R
EGISTER
(FIER) H
EX
A
DDRESS
: 0
X
nB05
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
5
SIG_ENB
R/W
0
Change in Signaling Bits Interrupt Enable
This bit permits the user to either enable or disable the “Change in Sig-
naling Bits” Interrupt, within the XRT86VL34 device. If the user enables
this interrupt, then the Receive T1 Framer block will generate an inter-
rupt when it detects a change in the any four signaling bits (A,B,C,D) in
any one of the 24 signaling channels. Users can read the signaling
change registers (address 0xn10D-0xn10F) to determine which signal-
ling channel has changed state.
0 - Disables the Change in Signaling Bits Interrupt
1 - Enables the Change in Signaling Bits Interrupt
N
OTE
:
This bit has no meaning when Robbed-Bit Signaling is disabled.
4
COFA_ENB
R/W
0
Change of Framing Alignment (COFA) Interrupt Enable
This bit permits the user to either enable or disable the “Change in FAS
Framing Alignment (COFA)” Interrupt, within the XRT86VL34 device. If
the user enables this interrupt, then the Receive T1 Framer block will
generate an interrupt when it detects a Change of Framing Alignment
Signal (e.g., the Framing bits have appeared to move to a different
location within the incoming T1 data stream).
0 - Disables the “Change of Framing Alignment (COFA)” Interrupt.
1 - Enables the “Change of Framing Alignment (COFA)” Interrupt.
3
OOF_ENB
R/W
0
Change in Out of Frame Defect Condition interrupt enable
This bit permits the user to either enable or disable the “Change in Out
of Frame Defect Condition” Interrupt, within the XRT86VL34 device. If
the user enables this interrupt, then the Receive T1 Framer block will
generate an interrupt in response to either one of the following condi-
tions.
1.
The instant that the Receive T1 Framer block declares the Out of
Frame defect condition.
2.
The instant that the Receive T1 Framer block clears the Out of
Frame defect condition.
0 – Disables the “Change in Out of Frame Defect Condition” Interrupt.
1 – Enables the “Change in Out of Frame Defect Condition” Interrupt.
2
FMD_ENB
R/W
0
Frame Mimic Detection Interrupt Enable
This bit permits the user to either enable or disable the “Frame Mimic
Detection” Interrupt, within the XRT86VL34 device. If the user enables
this interrupt, then the Receive T1 Framer block will generate an inter-
rupt when it detects the presence of Frame mimic bits (i.e., the payload
bits have appeared to mimic the framing bit pattern within the incoming
T1 data stream).
0 - Disables the “Frame Mimic Detection” Interrupt.
1 - Enables the “Frame Mimic Detection” Interrupt.
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