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參數(shù)資料
型號(hào)： XRT83L38IB-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 6/87頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 OCTAL 225BGA
標(biāo)準(zhǔn)包裝： 84
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 8/8
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT83L38
11
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.2
MICROPROCESSOR INTERFACE
SIGNAL NAME
LEAD #
TYPE
DESCRIPTION
HW_HOST
T10
I
Mode Control Input
This pin selects Hardware or Host mode. Leave this pin unconnected or tie “High”
to select Hardware mode.
For Host mode, this pin must be tied “Low”.
NOTE: Internally pulled “High” with a 50k
Ω resistor.
WR_R/W
EQC0
D7
I
Write Input (Read/Write) - Host mode:
Intel bus timing: A “Low” pulse on WR selects a write operation when CS pin is
“Low”.
Motorola bus timing: A “High” pulse on R/W selects a read operation and a “Low”
pulse on R/W selects a write operation when CS is “Low”.
Equalizer Control Input pin 0 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out.
NOTE: Internally pulled “Low” with a 50k
Ω resistor.
RD_DS
EQC1
C7
I
Read Input (Data Strobe) - Host mode
Intel bus timing: A “Low” pulse on RD selects a read operation when the CS pin is
“Low”.
Motorola bus timing: A “Low” pulse on DS indicates a read or write operation when
the CS pin is “Low”.
Equalizer Control Input pin 1 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out.
NOTE: Internally pulled “Low” with a 50k
Ω resistor.
ALE_AS
EQC2
A7
I
Address Latch Input (Address Strobe) - Host mode
Intel bus timing: The address inputs are latched into the internal register on the fall-
ing edge of ALE.
Motorola bus timing: The address inputs are latched into the internal register on
the falling edge of AS.
Equalizer Control Input pin 2 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out.
NOTE: Internally pulled “Low” with a 50k
Ω resistor.
CS
EQC3
B7
I
Chip Select Input - Host mode:
This signal must be “Low” in order to access the parallel port.
Equalizer Control Input pin 3 - Hardware mode:
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out.
NOTE: Internally pulled “Low” with a 50k
Ω resistor.
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