參數(shù)資料
型號(hào)： XRT83L38IB-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 43/87頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 OCTAL 225BGA
標(biāo)準(zhǔn)包裝： 84
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 8/8
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT83L38
45
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.2
MICROPROCESSOR PARALLEL INTERFACE
XRT83L38 is equipped with a microprocessor interface for easy device configuration. The parallel port of the
XRT83L38 is compatible with both Intel and Motorola address and data buses. The XRT83L38 has an 8-bit
address A[7:0] input and 8-bit bi-directional data bus D[7:0]. The signals required for a generic microprocessor
to access the internal registers are described in Table 16.
TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION
D[7:0]
Data Input (Output): 8 bits bi-directional Read/Write data bus for register access.
A[7:0]
Address Input: 8 bit address to select internal register location.
μPTS1
μPTS2
Microprocessor Type Select:
μPCLK
Microprocessor Clock Input: Input clock for synchronous microprocessor operation. Maximum
clock speed is 54MHz. This pin is internally pulled “Low” for asynchronous microprocessor operation
when no clock is present.
ALE_AS
Address Latch Input (Address Strobe):
-Intel bus timing, the address inputs are latched into the internal register on the falling edge of ALE.
-Motorola bus timing, the address inputs are latched into the internal register on the falling edge of
AS.
CS
Chip Select Input: This signal must be “Low” in order to access the parallel port.
RD_DS
Read Input (Data Strobe):
-Intel bus timing, a “Low” pulse on RD selects a read operation when CS pin is “Low”.
-Motorola bus timing, a “Low” pulse on DS indicates a read or write operation when CS pin is “Low”.
WR_R/W
Write Input (Read/Write):
-Intel bus timing, a “Low” pulse on WR selects a write operation when CS pin is “Low”.
-Motorola bus timing, a “High” pulse on R/W selects a read operation and a “Low” pulse on R/W
selects a write operation when CS pin is “Low”.
RDY_DTACK
Ready Output (Data Transfer Acknowledge Output):
-Intel bus timing, RDY is asserted “High” to indicate the XRT83L38 has completed a read or write
operation.
-Motorola bus timing, DTACK is asserted “Low” to indicate the XRT83L38 has completed a read or
write operation.
INT
Interrupt Output: This pin is asserted “Low” to indicate an interrupt caused by an alarm condition in
the device status registers. The activation of this pin can be blocked by setting the GIE bit to “0” in the
Command Control register.
μ PTS2
μ PTS1
0
1
0
μP Type
68 HC11, 8051, 80C188 (async.)
Mo torola 68K (async.)
Intel x86 (sync.)
Intel i960, Motorola 860 (sync.)
1
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