參數(shù)資料
型號： XRT79L74IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
中文描述： ATM NETWORK INTERFACE, PBGA456
封裝： 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-456
文件頁數(shù)： 31/70頁
文件大?。?/td> 547K
代理商： XRT79L74IB
PRELIMINARY
XRT79L74
REV. P1.0.0
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
29
K1
L2
F24
H26
RxOHFrame1/
RxHDLCDat1_4
RxOHFrame2/
RxHDLCDat2_4
RxOHFrame3/
RxHDLCDat3_4
RxOHFrame4/
RxHDLCDat4_4
O
O
O
O
Receive Overhead Data Interface - Framing Pulse indicator/Receive HDLC
Controller Data Bus - Bit 4 output:
The function of these output pins depend upon whether the XRT79L74 has
been configured to operate in the Clear-Channel Framer Mode or in the High-
Speed HDLC Controller Mode.
Clear-Channel Framer Mode - RxOHFrame:
These output pins pulse "High" whenever the Receive Overhead Data Output
Interface block outputs the first overhead bit of a new DS3 or E3 frame.
High-Speed HDLC Controller Mode - RxHDLCDat_4:
These output pins along with RxHDLCDatn_[3:0] and RxHDLCDatn_[7:5] func-
tions as the Receive HDLC Controller byte wide output data bus. The Receive
HDLC Controller will output the contents of all HDLC frames via this output data
bus, upon the rising edge of the RxHDLCClk output signals. Hence, the user’s
local terminal equipment should be designed/configured to sample this data
upon the falling edge of the RxHDLCClk output clock signals.
N3
J26
R4
M22
RxFrame1
RxFrame2
RxFrame3
RxFrame4
0
O
O
O
Receive Boundary of DS3 or E3 Frame Output indicator:
The function of these output pins depend upon whether or not the XRT79L74 is
operating in the Clear-Channel Framer/Nibble-Parallel Mode.
Clear-Channel Framer/Nibble-Parallel Mode:
The Receive Section of the XRT79L74 will pulse these output pins "High" for
one nibble period, when the Receive Payload Data Output interface block is
driving the very first nibble of a given DS3 or E3 frame, on the RxNibn[3:0] out-
put pins.
Clear-Channel Framer/Serial Mode:
The Receive Section of the XRT79L74 will pulse these output pins "High" for
one bit period, when the Receive Payload Data Output interface block is driving
the very first bit of a given DS3 or E3 frame, on the RxSer output pin.
All Other Modes:
The Receive Section of the XRT79L74 will pulse these output pins "High" when
the Receive DS3/E3 Framer block is processing the first bit within a new DS3 or
E3 frame.
B1
D21
E4
B24
RxCellRxed1
RxCellRxed2
RxCellRxed3
RxCellRxed4
O
O
O
O
Receive Cell Processor - Cell Received Indicator:
These output pins pulse "High" each time the Receive Cell Processor receives
a new cell from the Receive PLCP Processor or the Receive DS3/E3 Framer
block.
These output pins are only active if the XRT79L74 has been configured to oper-
ate in the ATM UNI Mode.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
XRT8000ID Clock Synchronizer/Adapter for Communications
XRT8000 Clock Synchronizer/Adapter for Communications(用于通訊的時鐘同步設(shè)備/調(diào)整器)
XRT8001 WAN Clock for T1 and E1 Systems
XRT8001ID WAN Clock for T1 and E1 Systems
XRT8001IP WAN Clock for T1 and E1 Systems
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT8000 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications
XRT8000_06 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications
XRT8000D 制造商:EXAR 制造商全稱:EXAR 功能描述:CLOCK SYNCHRONIZER/ADAPTER FOR COMMUNICATIONS
XRT8000ES 功能描述:鎖相環(huán) - PLL WAN CLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
XRT8000ID 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*