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XRT79L71
PRELIMINARY
115
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
STEP 3c - Enable the Transmit FEAC Interrupt at the Source Level
The user can enable the Transmit FEAC Message Interrupt by setting bit 4 (Tx FEAC Interrupt Enable) within
the Transmit DS3 FEAC Configuration & Status register to "1", as illustrated below.
If the Transmit FEAC Message Interrupt is enabled, then the channel will generate an interrupt as soon as the
Transmit FEAC Controller block has completed its 10th transmission of the FEAC Message.
STEP 4 - Initiate the Transmission of the FEAC Message
The user can initiate the transmission of the FEAC message residing in the Transmit DS3 FEAC register by
inducing a "0" to "1" transition in Bit 1 (Tx FEAC Go) within the Transmit DS3 FEAC Configuration and Status
Register. This can be accomplished by writing a "1" to bit 1 of the Transmit DS3 FEAC Configuration and
Status register, as depicted below.
NOTES:
1.
While executing this particular write command, the user should write a 000xx110b to the Transmit DS3 FEAC
Configuration and Status Register. The user must insure that a "1" is also being written to Bit 2 of the register, in
order to keep the Transmit FEAC Controller block enabled.
2.
The Transmit FEAC Controller block requires a "0" to "1" transition within Bit 1 (Tx FEAC Go).
Therefore,
sometime after setting Bit 1 to "1", the user must follow up and set this bit-field back to "0".
At this point, the Transmit FEAC Controller block will proceed to transmit the 16 bit FEAC code via the
outbound DS3 frame message repeatedly for 10 consecutive times. This process will require a total of 160
DS3 frame periods. During this process the Tx FEAC Busy bit (Bit 0) will be asserted, indicating that the
Block Interrupt Enable Register (Address = 0x1104)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive DS3/E3
Framer Block
Interrupt Enable
Receive PLCP
Processor Block
Interrupt Enable
Unused
Transmit DS3/
E3 Framer Block
Interrupt Enable
One Second
Interrupt Enable
R/W
R/O
R/W
X
0
1
X
Transmit DS3 FEAC Configuration and Status Register (Address = 0x1131)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Tx FEAC
Interrupt
Enable
Tx FEAC
Interrupt
Status
Tx FEAC
Enable
Tx FEAC Go
Tx FEAC
Busy
R/O
R/W
R/O
R/W
R/O
0
1
X
1
0
Transmit DS3 FEAC Configuration and Status Register (Address = 0x1131)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
Tx FEAC
Interrupt
Enable
Tx FEAC
Interrupt
Status
Tx FEAC
Enable
Tx FEAC Go
Tx FEAC
Busy
R/O
R/W
R/O
R/W
R/O
0
X
1
0->1
0