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PRELIMINARY
XRT79L71
108
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
If Method 2 is used the users system must be designed such that the System-Side Terminal Equipment will be
interfaced to the Transmit Overhead Data Input Interface block, in a manner as presented below in Figure 46.
Method 2 Operation of the Transmit Overhead Data Input Interface Block
Tto operate the Transmit Overhead Data Input Interface block per Method 2, design/configure the System-Side
Terminal Equipment to continuously execute the following tasks.
TASK # 1: The System-Side Terminal Equipment must sample the states of both the TxOHFrame and the
TxOHEnable output pins from the XRT79L71 upon the falling edge of the TxInClk clock input signal. The
XRT79L71 will pulse the TxOHEnable output pin "High" for one TxInClk period, just prior to the instant that the
Transmit Overhead Data Input Interface block is processing an overhead bit. Therefore, if the System-Side
Terminal Equipment samples the TxOHEnable output pin "High", then it knows that an overhead bit insertion
opportunity via the Transmit Overhead Data Input Interface block is just about to occur. If the System-Side
Terminal Equipment samples both the TxOHEnable and the TxOHFrame output pins "High" at the same time,
then it knows that the Transmit Overhead Data Input Interface block is just about to process the very first
overhead bit (in this case an X bit) within a new DS3 frame.
TASK # 2: As the System-Side Terminal Equipment samples the TxOHEnable and TxOHFrame signals, it
must also keep track of the number of times that the TxOHEnable output pin has been sampled "High" since
the last time both the TxOHEnable and the TxOHFrame output pins have been sampled "High". By doing this,
the System-Side Terminal Equipment will be able to keep track of which overhead bits are currently being
processed by the Transmit Overhead Data Input Interface block at any given TxOHEnable assertion. When
the System-Side Terminal Equipment knows which overhead bit it being processed within a given TxOHEnable
assertion period, it can decide when to insert the appropriate bit-value into the Transmit Overhead Data Input
Interface block and in-turn, force the Transmit DS3/E3 Framer block to insert this bit into the appropriate
overhead bit-position within the outbound DS3 data-stream.
From all of this, the System-Side Terminal
Equipment will know when it should assert the TxOHIns input pin and placd the appropriate value on the TxOH
input pin of the XRT79L71.
Table 21 relates the number of TxOHEnable output pulses that have occurred since both the TxOHFrame and
the TxOHEnable pins were sampled "High", to the DS3 Overhead Bit being processed by the Transmit
Overhead Data Input Interface block. This user can use this table as a guide for inserting the appropriate
overhead bits, within the outbound DS3 data-stream, for Method 2.
FIGURE 46. ILLUSTRATION ON HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE TRANSMIT
OVERHEAD DATA INPUT INTERFACE BLOCK WHEN USING METHOD 2
System-Side Terminal
Equipment
XRT79L71 DS3/E3 Framer
DS3_OH_Out
DS3_OH_Enable
Tx_Start_of_Frame
TxOHEnable
TxOHFrame
TxOHIns
44.736 MHz Clock Source
TxInClk
TxOH
Insert_OH