參數(shù)資料
型號： XRT75VL00D
廠商： Exar Corporation
英文描述： E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER
文件頁數(shù)： 67/92頁
文件大小： 836K
代理商： XRT75VL00D
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
4
Figure 53. Illustration of 87-3 Cancel Pointer Adjustment Scenario ............................................................... 72
9.5.8 Continuous Pattern ............................................................................................................................ 73
9.5.9 Continuous Add ................................................................................................................................ 73
Figure 54. Illustration of Continuous Periodic Pointer Adjustment Scenario ................................................. 73
9.5.10 Continuous Cancel .......................................................................................................................... 74
Figure 55. Illustration of Continuous-Add Pointer Adjustment Scenario ......................................................... 74
Figure 56. Illustration of Continuous-Cancel Pointer Adjustment Scenario .................................................... 74
9.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ............................................... 75
9.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM APPLICATION ...
75
9.7.1 Intrinsic Jitter Test results ................................................................................................................ 75
TABLE 19: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ....... 75
9.7.2 Wander Measurement Test Results ................................................................................................. 76
9.8 DESIGNING WITH THE LIU ................................................................................................................................. 76
9.8.1 How to design and configure the LIU to permit a system to meet the above-mentioned Intrinsic
Jitter and Wander requirements ...................................................................................................................................... 76
Figure 57. Illustration of the LIU being connected to a Mapper IC for SONET De-Sync Applications ........... 76
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................... 77
CHANNEL 1 ADDRESS LOCATION = 0X0E ........................................... 77
CHANNEL 2 ADDRESS LOCATION = 0X16 ........................................... 77
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................... 78
CHANNEL 1 ADDRESS LOCATION = 0X0E ................................................ 78
CHANNEL 2 ADDRESS LOCATION = 0X16 ................................................. 78
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07 ................................. 78
CHANNEL 1 ADDRESS LOCATION = 0X0F .................................... 78
CHANNEL 2 ADDRESS LOCATION = 0X17 .................................... 78
9.8.2 Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to
routing this DS3 Clock and Data-Signals to the Transmit Inputs of the LIU ............................................................... 79
SOME NOTES PRIOR TO STARTING THIS DISCUSSION: 79
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 79
CHANNEL 1 ADDRESS LOCATION = 0X0F .............................. 79
CHANNEL 2 ADDRESS LOCATION = 0X17 .............................. 79
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 79
CHANNEL 1 ADDRESS LOCATION = 0X0F ............................. 79
CHANNEL 2 ADDRESS LOCATION = 0X17 ............................. 79
OUR PRE-PROCESSING RECOMMENDATIONS 80
Figure 58. Illustration of MINOR PATTERN P1 .............................................................................................. 80
Figure 59. Illustration of MINOR PATTERN P2 .............................................................................................. 81
Figure 60. Illustration of Procedure which is used to Synthesize MAJOR PATTERN A ................................ 81
Figure 61. Illustration of MINOR PATTERN P3 .............................................................................................. 82
Figure 62. Illustration of Procedure which is used to Synthesize PATTERN B ............................................. 82
9.8.3 How does the LIU permit the user to comply with the SONET APS Recovery Time requirements
of 50ms (per Telcordia GR-253-CORE)? ......................................................................................................................... 83
Figure 63. Illustration of the SUPER PATTERN which is output via the "OC-N to DS3" Mapper IC .............. 83
Figure 64. Simple Illustration of the LIU being used in a SONET De-Synchronizer" Application ................... 83
TABLE 20: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET ............................................ 84
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 84
CHANNEL 1 ADDRESS LOCATION = 0X0F ............................. 84
CHANNEL 2 ADDRESS LOCATION = 0X17 ............................. 84
9.8.4 How should one configure the LIU, if one needs to support "Daisy-Chain" Testing at the end Cus-
tomer’s site? ..................................................................................................................................................................... 85
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 85
CHANNEL 1 ADDRESS LOCATION = 0X0F .................................... 85
CHANNEL 2 ADDRESS LOCATION = 0X17 .................................... 85
ORDERING INFORMATION ............................................................................................................................ 86
PACKAGE DIMENSIONS ................................................................................................. 86
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75VL00D_08 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET
XRT75VL00D1V-F 制造商:Exar Corporation 功能描述:
XRT75VL00DES 功能描述:時鐘合成器/抖動清除器 1CHT3/E3/STS1LIU+ DESYNC 3.3V DRV VER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75VL00DIV 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75VL00DIV-F 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/SONET DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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