TABLE
參數(shù)資料
型號(hào)： XRT75R12IB
廠商： Exar Corporation
文件頁(yè)數(shù)： 74/90頁(yè)
文件大小： 0K
描述： IC LIU E3/DS3/STS-1 12CH 420TBGA
標(biāo)準(zhǔn)包裝： 40
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 12/12
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 420-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 420-TBGA（35x35）
包裝： 托盤
XRT75R12
73
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 35: XRT75R12 REGISTER MAP SHOWING TRANSMIT CONTROL REGISTERS (TC_n)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Internal
Transmit
Drive Monitor
Insert PRBS
Error
Reserved
TAOS
TxCLKINV
TxLEV
R/W
TABLE 36: TRANSMIT CONTROL REGISTER - CHANNEL n ADDRESS LOCATION = 0XM4
(n = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7 - 6
Reserved
5
Internal Transmit
Drive Monitor
Enable
R/W
Internal Transmit Drive Monitor Enable - Channel_n:
This READ/WRITE bit-field is used to configure the Transmit Section of
Channel_n to either internally or externally monitor the TTIP_n and
TRING_n output pins for bipolar pulses, in order to determine whether to
declare the Transmit DMO Alarm condition.
If the user configures the Transmit Section to externally monitor the TTIP_n
and TRING_n output pins (for bipolar pulses) then the user must connect
the MTIP_n and MRING_n input pins to their corresponding TTIP_n and
TRING_n output pins (via a 270 ohm series resistor).
If the user configures the Transmit Section to internally monitor the TTIP_n
and TRING_n output pins (for bipolar pulses), the user does NOT need to
conect the MTIP_n and MRING_n input pins. This monitoring will be per-
formed internally at the TTIP_n and TRING_n pads.
0 - Configures the Transmit Drive Monitor to externally monitor the TTIP_n
and TRING_n output pins for bipolar pulses.
1 - Configures the Transmit Drive Monitor to internally monitor the TTIP_n
and TRING_n output pins for bipolar pulses.
4
Insert PRBS Error
R/W
Insert PRBS Error - Channel_n:
A "0 to 1" transition within this bit-field causes the PRBS Generator (within
the Transmit Section of Channel_n) to generate a single bit error within the
outbound PRBS pattern-stream.
NOTES:
1.
This bit-field is only active if the PRBS Generator and Receiver
have been enabled within the corresponding Channel.
2.
After writing the "1" into this register, the user must execute a write
operation to clear this particular register bit to "0" in order to
facilitate the next "0 to 1" transition in this bit-field.
3
Reserved
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XRT75VL00 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00_08 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00D 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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