參數(shù)資料
型號(hào)： XRT75R12IB
廠商： Exar Corporation
文件頁(yè)數(shù)： 2/90頁(yè)
文件大小： 0K
描述： IC LIU E3/DS3/STS-1 12CH 420TBGA
標(biāo)準(zhǔn)包裝： 40
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 12/12
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 420-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 420-TBGA（35x35）
包裝： 托盤
XRT75R12
7
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
F23
AC26
F24
U23
L23
T24
L4
T3
F3
U4
F4
AC1
RxNEG/LCV0
RxNEG/LCV1
RxNEG/LCV2
RxNEG/LCV3
RxNEG/LCV4
RxNEG/LCV5
RxNEG/LCV6
RxNEG/LCV7
RxNEG/LCV8
RxNEG/LCV9
RxNEG/LCV10
RxNEG/LCV11
O
Receive Negative Data Output/Line Code Violation
The function of these pins depends on whether the XRT75R12 is configured in
Single Rail or Dual Rail mode.
Dual-Rail Mode - Receive Negative Polarity Data Output
In the Dual-Rail Mode, all negative-polarity data will be output via this pin. The
positive-polarity data will be output via the corresponding RxPOS_n output pin.
In other words, the Receive Section of the corresponding Channel will pulse this
output pin "High" for one period of RxCLK_n anytime it receives a negative-
polarity pulse via the RTIP/RRING input pins.
The data output via this pin is updated upon the active edge of the RCLK_n
output clock signal.
Single-Rail Mode - Line Code Violation Indicator Output
In the Single-Rail Mode, this output pin will function as the Line Code Violation
indicator output.
In this configuration, the Receive Section of the Channel will pulse this output
pin "High" for at least one RCLK period whenever it detects either an LCV (Line
Code Violation) or an EXZ (Excessive Zero Event).
The data that is output via this pin is updated upon the active edge of the
RCLK_n output clock signal.
E24
AC25
J23
V23
K24
T23
K3
T4
J4
V4
E3
AC2
RxCLK0
RxCLK1
RxCLK2
RxCLK3
RxCLK4
RxCLK5
RxCLK6
RxCLK7
RxCLK8
RxCLK9
RxCLK10
RxCLK11
O
Receive Clock Output
This output pin functions as the Receive or recovered clock signal. All Receive
(or recovered) data will output via the RxPOS_n and RxNEG_n outputs upon
the active edge of this clock signal.
Additionally, if the device/channel has been configured to operate in the Single-
Rail Mode, then the RNEG_n/LCV_n output pins will also be updated upon the
active edge of this clock signal.
SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75R12IB-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R12IB-L 功能描述:LIN 收發(fā)器 Attenuator RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
XRT75VL00 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00_08 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00D 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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