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XRT75R12
69
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
TABLE 33: XRT75R12 REGISTER MAP SHOWING ALARM STATUS REGISTERS (AS_n)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Loss of PRBS
Pattern Sync
Digital LOS
Defect
Declared
Analog LOS
Defect
Declared
FL
(FIFO Limit)
Alarm
Declared
Receive LOL
Defect
Declared
Receive LOS
Defect
Declared
Transmit
DMO
Condition
R/O
TABLE 34: ALARM STATUS REGISTER - CHANNEL n ADDRESS LOCATION = 0XM3
(n = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7
Reserved
6
Loss of PRBS Pat-
tern Lock
R/O
Loss of PRBS Pattern Lock Indicator:
This READ-ONLY bit-field indicates whether or not the PRBS Receiver
(within the Receive Section of Channel n) is declaring PRBS Lock within the
incoming PRBS pattern.
If the PRBS Receiver detects a very large number of bit-errors within its
incoming data-stream, then it will declare the Loss of PRBS Lock Condition.
Conversely, if the PRBS Receiver were to detect its pre-determined PRBS
pattern with the incoming DS3, E3 or STS-1 data-stream, (with little or no bit
errors) then the PRBS Receiver will clear the Loss of PRBS Lock condition.
0 - Indicates that the PRBS Receiver is currently declaring the PRBS Lock
condition within the incoming DS3, E3 or STS-1 data-stream.
1 - Indicates that the PRBS Receiver is currently declaring the Loss of
PRBS Lock condition within the incoming DS3, E3 or STs-1 data-stream.
NOTE: This register bit is only valid if all of the following are true.
a. The PRBS Generator block (within the Transmit Section of the Chip is
enabled).
b. The PRBS Receiver is enabled.
c. The PRBS Pattern (that is generated by the PRBS Generator) is
somehow looped back into the Receive Path (via the Line-Side) and
in-turn routed to the receive input of the PRBS Receiver.
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