參數(shù)資料
型號： XRT75R12DIB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： DATACOM, PCM TRANSCEIVER, PBGA420
封裝： 35 X 35 MM, TBGA-420
文件頁數(shù)： 5/131頁
文件大小： 717K
代理商： XRT75R12DIB
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
PRELIMINARY
REV. P1.0.1
III
T
ABLE
22: T
HE
ABOVE
IS
: C
HANNEL
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- CR97 (A
DDRESS
L
OCATION
= 0
X
61).................................. 63
T
ABLE
23: C
HANNEL
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- CR225 (A
DDRESS
L
OCATION
= 0
X
E1)....................................................... 63
T
ABLE
24: D
EVICE
/P
ART
N
UMBER
R
EGISTER
- CR110 (A
DDRESS
L
OCATION
= 0
X
6E) ........................................................................... 64
T
ABLE
25: C
HIP
R
EVISION
N
UMBER
R
EGISTER
- CR111 (A
DDRESS
L
OCATION
= 0
X
6F) ......................................................................... 64
THE PER-CHANNEL REGISTERS........................................................................................................................... 65
REGISTER DESCRIPTION - PER CHANNEL REGISTERS....................................................................................66
T
ABLE
26: XRT75R12D R
EGISTER
MAP
SHOWING
I
NTERRUPT
E
NABLE
R
EGISTERS
(IER_
N
)............................................................... 66
T
ABLE
27: S
OURCE
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- C
HANNEL
N
A
DDRESS
L
OCATION
= 0
XM
1 .................................................... 66
T
ABLE
28: XRT75R12D R
EGISTER
MAP
SHOWING
I
NTERRUPT
S
TATUS
R
EGISTERS
(ISR_
N
)............................................................... 68
T
ABLE
29: S
OURCE
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- C
HANNEL
N
A
DDRESS
L
OCATION
= 0
XM
2 .................................................... 68
T
ABLE
30: XRT75R12D R
EGISTER
MAP
SHOWING
A
LARM
S
TATUS
R
EGISTERS
(AS_
N
)........................................................................ 70
T
ABLE
31: A
LARM
S
TATUS
R
EGISTER
- C
HANNEL
N
A
DDRESS
L
OCATION
= 0
XM
3................................................................................... 70
T
ABLE
32: XRT75R12D R
EGISTER
MAP
SHOWING
T
RANSMIT
C
ONTROL
R
EGISTERS
(TC_
N
)................................................................ 74
T
ABLE
33: T
RANSMIT
C
ONTROL
R
EGISTER
- C
HANNEL
N
A
DDRESS
L
OCATION
= 0
XM
4 ........................................................................... 74
T
ABLE
34: XRT75R12D R
EGISTER
MAP
SHOWING
R
ECEIVE
C
ONTROL
R
EGISTERS
(RC_
N
).................................................................. 76
T
ABLE
35: R
ECEIVE
C
ONTROL
R
EGISTER
- C
HANNEL
N
A
DDRESS
L
OCATION
= 0
XM
5 ............................................................................. 76
T
ABLE
36: XRT75R12D R
EGISTER
MAP
SHOWING
C
HANNEL
C
ONTROL
R
EGISTERS
(CC_
N
)................................................................. 77
T
ABLE
37: C
HANNEL
C
ONTROL
R
EGISTER
- C
HANNEL
N
A
DDRESS
L
OCATION
= 0
XM
6............................................................................ 77
T
ABLE
38: XRT75R12D R
EGISTER
MAP
SHOWING
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTERS
(JA_
N
)................................................. 80
T
ABLE
39: J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
N
A
DDRESS
L
OCATION
= 0
XM
7 ........................................................... 80
T
ABLE
40: XRT75R12D R
EGISTER
MAP
SHOWING
E
RROR
C
OUNTER
MSB
YTE
R
EGISTERS
(EM_
N
)..................................................... 81
T
ABLE
41: E
RROR
C
OUNTER
MSB
YTE
R
EGISTER
- C
HANNEL
N
A
DDRESS
L
OCATION
= 0
XM
A................................................................. 81
T
ABLE
42: XRT75R12D R
EGISTER
MAP
SHOWING
E
RROR
C
OUNTER
LSB
YTE
R
EGISTERS
(EL_
N
)....................................................... 82
T
ABLE
43: E
RROR
C
OUNTER
LSB
YTE
R
EGISTER
- C
HANNEL
N
A
DDRESS
L
OCATION
= 0
XM
B.................................................................. 82
T
ABLE
44: XRT75R12D R
EGISTER
MAP
SHOWING
E
RROR
C
OUNTER
H
OLDING
R
EGISTERS
(EH_
N
) ..................................................... 82
T
ABLE
45: E
RROR
C
OUNTER
H
OLDING
R
EGISTER
- C
HANNEL
N
A
DDRESS
L
OCATION
= 0
XM
C................................................................ 83
8.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ...............................................................85
8.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ........................... 85
F
IGURE
37. A S
IMPLE
I
LLUSTRATION
OF
A
DS3
SIGNAL
BEING
MAPPED
INTO
AND
TRANSPORTED
OVER
THE
SONET N
ETWORK
............... 86
8.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................. 87
8.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................. 87
F
IGURE
38. A S
IMPLE
I
LLUSTRATION
OF
THE
SONET STS-1 F
RAME
..................................................................................................... 88
F
IGURE
39. A S
IMPLE
I
LLUSTRATION
OF
THE
STS-1 F
RAME
S
TRUCTURE
WITH
THE
TOH
AND
THE
E
NVELOPE
C
APACITY
B
YTES
D
ESIGNATED
89
F
IGURE
40. T
HE
B
YTE
-F
ORMAT
OF
THE
TOH
WITHIN
AN
STS-1 F
RAME
................................................................................................. 90
F
IGURE
41. T
HE
B
YTE
-F
ORMAT
OF
THE
TOH
WITHIN
AN
STS-1 F
RAME
................................................................................................. 91
F
IGURE
42. I
LLUSTRATION
OF
THE
B
YTE
S
TRUCTURE
OF
THE
STS-1 SPE............................................................................................. 92
F
IGURE
43. A
N
I
LLUSTRATION
OF
T
ELCORDIA
GR-253-CORE’
S
R
ECOMMENDATION
ON
HOW
MAP
DS3
DATA
INTO
AN
STS-1 SPE......... 93
F
IGURE
44. A S
IMPLIFIED
"B
IT
-O
RIENTED
" V
ERSION
OF
T
ELCORDIA
GR-253-CORE’
S
R
ECOMMENDATION
ON
HOW
TO
MAP
DS3
DATA
INTO
AN
STS-1 SPE.......................................................................................................................................................................... 93
8.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS......................................... 94
F
IGURE
45. A S
IMPLE
I
LLUSTRATION
OF
A
DS3 D
ATA
-S
TREAM
BEING
M
APPED
INTO
AN
STS-1 SPE,
VIA
A
PTE .................................... 95
F
IGURE
46. A
N
I
LLUSTRATION
OF
THE
STS-1 SPE
TRAFFIC
THAT
WILL
BE
GENERATED
BY
THE
"S
OURCE
" PTE,
WHEN
MAPPING
IN
A
DS3
SIGNAL
THAT
HAS
A
BIT
RATE
OF
44.736M
BPS
+ 1
PPM
,
INTO
AN
STS-1
SIGNAL
.................................................................................. 96
8.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS .............................................................................. 98
8.3.1 THE CONCEPT OF AN STS-1 SPE POINTER........................................................................................................... 98
F
IGURE
47. A
N
I
LLUSTRATION
OF
THE
STS-1 SPE
TRAFFIC
THAT
WILL
BE
GENERATED
BY
THE
S
OURCE
PTE,
WHEN
MAPPING
A
DS3
SIGNAL
THAT
HAS
A
BIT
RATE
OF
44.736M
BPS
- 1
PPM
,
INTO
AN
STS-1
SIGNAL
................................................................................... 98
F
IGURE
48. A
N
I
LLUSTRATION
OF
AN
STS-1 SPE
STRADDLING
ACROSS
TWO
CONSECUTIVE
STS-1
FRAMES
........................................... 99
8.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK................................................................................ 100
F
IGURE
49. T
HE
B
IT
-
FORMAT
OF
THE
16-B
IT
W
ORD
(
CONSISTING
OF
THE
H1
AND
H2
BYTES
)
WITH
THE
10
BITS
,
REFLECTING
THE
LOCATION
OF
THE
J1
BYTE
,
DESIGNATED
.................................................................................................................................................. 100
F
IGURE
50. T
HE
R
ELATIONSHIP
BETWEEN
THE
C
ONTENTS
OF
THE
"P
OINTER
B
ITS
" (
E
.
G
.,
THE
10-
BIT
EXPRESSION
WITHIN
THE
H1
AND
H2
BYTES
)
AND
THE
L
OCATION
OF
THE
J1 B
YTE
WITHIN
THE
E
NVELOPE
C
APACITY
OF
AN
STS-1 F
RAME
................................................ 100
8.3.3 CAUSES OF POINTER ADJUSTMENTS................................................................................................................. 101
F
IGURE
51. A
N
I
LLUSTRATION
OF
AN
STS-1
SIGNAL
BEING
PROCESSED
VIA
A
S
LIP
B
UFFER
.................................................................. 102
F
IGURE
52. A
N
I
LLUSTRATION
OF
THE
B
IT
F
ORMAT
WITHIN
THE
16-
BIT
WORD
(
CONSISTING
OF
THE
H1
AND
H2
BYTES
)
WITH
THE
"I"
BITS
DES
-
IGNATED
............................................................................................................................................................................. 103
F
IGURE
53. A
N
I
LLUSTRATION
OF
THE
B
IT
-F
ORMAT
WITHIN
THE
16-
BIT
WORD
(
CONSISTING
OF
THE
H1
AND
H2
BYTES
)
WITH
THE
"D"
BITS
DES
-
IGNATED
............................................................................................................................................................................. 104
8.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS ............................................................................. 105
8.4 CLOCK GAPPING JITTER ........................................................................................................................... 105
F
IGURE
54. I
LLUSTRATION
OF
THE
T
YPICAL
A
PPLICATIONS
FOR
THE
LIU
IN
A
SONET D
E
-S
YNC
A
PPLICATION
...................................... 105
8.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE)
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