- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1977 > XRT75R12DIB-L (Exar Corporation)IC LIU E3/DS3/STS-1 12CH 420TBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | XRT75R12DIB-L |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 90/133頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 12/12 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 420-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 420-TBGA（35x35） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁當(dāng)前第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁
XRT75R12D
IV
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
FIGURE 56. ILLUSTRATION OF BURST OF POINTER ADJUSTMENT SCENARIO ......................................................................................... 110
8.5.4 PHASE TRANSIENTS............................................................................................................................................... 110
FIGURE 57. ILLUSTRATION OF "PHASE-TRANSIENT" POINTER ADJUSTMENT SCENARIO .......................................................................... 110
8.5.5 87-3 PATTERN .......................................................................................................................................................... 111
FIGURE 58. AN ILLUSTRATION OF THE 87-3 CONTINUOUS POINTER ADJUSTMENT PATTERN .................................................................. 111
8.5.6 87-3 ADD ................................................................................................................................................................... 111
FIGURE 59. ILLUSTRATION OF THE 87-3 ADD POINTER ADJUSTMENT PATTERN..................................................................................... 112
8.5.7 87-3 CANCEL ............................................................................................................................................................ 112
FIGURE 60. ILLUSTRATION OF 87-3 CANCEL POINTER ADJUSTMENT SCENARIO .................................................................................... 112
8.5.8 CONTINUOUS PATTERN ......................................................................................................................................... 113
FIGURE 61. ILLUSTRATION OF CONTINUOUS PERIODIC POINTER ADJUSTMENT SCENARIO .................................................................... 113
8.5.9
CONTINUOUS ADD ................................................................................................................................................. 113
FIGURE 62. ILLUSTRATION OF CONTINUOUS-ADD POINTER ADJUSTMENT SCENARIO ............................................................................. 114
8.5.10 CONTINUOUS CANCEL ......................................................................................................................................... 114
FIGURE 63. ILLUSTRATION OF CONTINUOUS-CANCEL POINTER ADJUSTMENT SCENARIO ....................................................................... 114
8.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ................................ 115
8.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM
APPLICATION .............................................................................................................................................. 115
8.7.1 INTRINSIC JITTER TEST RESULTS........................................................................................................................ 115
TABLE 44: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ......................................... 115
8.7.2 WANDER MEASUREMENT TEST RESULTS.......................................................................................................... 116
8.8 DESIGNING WITH THE LIU ......................................................................................................................... 116
8.8.1 HOW TO DESIGN AND CONFIGURE THE LIU TO PERMIT A SYSTEM TO MEET THE ABOVE-MENTIONED INTRIN-
SIC JITTER AND WANDER REQUIREMENTS........................................................................................................... 116
FIGURE 64. ILLUSTRATION OF THE LIU BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLICATIONS .............................. 116
TABLE 45: CHANNEL CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM6 (M = 0-5 & 8-D) (N = [0:11]) ............................... 117
TABLE 46: CHANNEL CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM6 (M = 0-5 & 8-D) (N = [0:11]) ............................... 117
TABLE 47: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7........................................................... 118
TABLE 48: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7........................................................... 118
TABLE 49: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7........................................................... 119
8.8.2 RECOMMENDATIONS ON PRE-PROCESSING THE GAPPED CLOCKS (FROM THE MAPPER/ASIC DEVICE) PRIOR
TO ROUTING THIS DS3 CLOCK AND DATA-SIGNALS TO THE TRANSMIT INPUTS OF THE LIU ...................... 119
FIGURE 65. ILLUSTRATION OF MINOR PATTERN P1 ......................................................................................................................... 120
FIGURE 66. ILLUSTRATION OF MINOR PATTERN P2 ......................................................................................................................... 120
FIGURE 67. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE MAJOR PATTERN A....................................................... 121
FIGURE 68. ILLUSTRATION OF MINOR PATTERN P3 ......................................................................................................................... 121
FIGURE 69. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE PATTERN B ................................................................... 122
FIGURE 70. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC ................................... 122
FIGURE 71. SIMPLE ILLUSTRATION OF THE LIU BEING USED IN A SONET DE-SYNCHRONIZER" APPLICATION......................................... 123
8.8.3 HOW DOES THE LIU PERMIT THE USER TO COMPLY WITH THE SONET APS RECOVERY TIME REQUIREMENTS
OF 50MS (PER TELCORDIA GR-253-CORE)? .......................................................................................................... 123
TABLE 50: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET ............................................................................. 123
TABLE 51: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7........................................................... 124
8.8.4 HOW SHOULD ONE CONFIGURE THE LIU, IF ONE NEEDS TO SUPPORT "DAISY-CHAIN" TESTING AT THE END
CUSTOMER'S SITE? ................................................................................................................................................... 124
TABLE 52: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N, ADDRESS LOCATION; 0XM7........................................................... 125
9.0 ELECTRICAL CHARACTERISTICS ..................................................................................................126
TABLE 53: ABSOLUTE MAXIMUM RATINGS ........................................................................................................................................... 126
TABLE 54: DC ELECTRICAL CHARACTERISTICS:................................................................................................................................... 126
ORDERING INFORMATION .................................................................................................................128
PACKAGE DIMENSIONS - ............................................................................................................................................ 128
REVISION HISTORY .................................................................................................................................................... 129
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT75R12IB-L | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| XRT75VL00DIV | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| XRT75VL00IV-F | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| XRT79L71IB-F | IC LIU/FRAMER DS3/E3 1CH 208BGA |
| XRT81L27IV-F | IC LIU EI 7CH 3.3V 128TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75R12ES | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 12CH T3/E3/STS1LIUJA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75R12IB | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 12CH E3/DS3/STS W/JITTER R3 TECH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75R12IB-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75R12IB-L | 功能描述:LIN 收發(fā)器 Attenuator RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8 |
| XRT75VL00 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。