TABLE
參數(shù)資料
型號： XRT75R12DIB-L
廠商： Exar Corporation
文件頁數(shù)： 120/133頁
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 12CH 420TBGA
標準包裝： 40
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 12/12
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 420-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 420-TBGA（35x35）
包裝： 托盤
XRT75R12D
83
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE 36: XRT75R12D REGISTER MAP SHOWING JITTER ATTENUATOR CONTROL REGISTERS (JA_N) (N = [0:11])
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
JA RESET
Ch_n
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
R/W
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM7 (M = 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7 - 4
Reserved
3
JA RESET Ch_n
R/W
Jitter Attenuator RESET - Channel_n:
Writing a "0 to 1" transition within this bit-field will configure the Jitter Attenu-
ator (within Channel_n) to execute a RESET operation.
Whenever the user executes a RESET operation, then following will occur.
The READ and WRITE pointers (within the Jitter Attenuator FIFO) will be
reset to their default values.
The contents of the Jitter Attenuator FIFO will be flushed.
NOTE: The user must follow up any "0 to 1" transition with the appropriate
write operate to set this bit-field back to "0", in order to resume
normal operation with the Jitter Attenuator.
2
JA1 Ch_n
R/W
Jitter Attenuator Configuration Select Input - Bit 1:
This READ/WRITE bit-field, along with Bit 0 (JA0 Ch_n) is used to do any of
the following.
To enable or disable the Jitter Attenuator corresponding to Channel_n.
To select the FIFO Depth for the Jitter Attenuator within Channel_n.
The relationship between the settings of these two bit-fields and the Enable/
Disable States, and FIFO Depths is presented below.
1
JA in Tx Path Ch_n
R/W
Jitter Attenuator in Transmit/Receive Path Select Bit:
This input pin is used to configure the Jitter Attenuator (within Channel_n) to
operate in either the Transmit or Receive path, as described below.
0 - Configures the Jitter Attenuator (within Channel_n) to operate in the
Receive Path.
1 - Configures the Jitter Attenuator (within Channel_n) to operate in the
Transmit Path.
0
JA0 Ch_n
R/W
Jitter Attenuator Configuration Select Input - Bit 0:
See the description for Bit 2 (JA1 Ch_n).
JA0
JA1
Jitter Attenuator Mode
1
Disabled
1
0
SONET/SDH De-Sync Mode
0
1
FIFO Depth = 32 bits
0
FIFO Depth = 16 bits
相關(guān)PDF資料
PDF描述
XRT75R12IB-L IC LIU E3/DS3/STS-1 12CH 420TBGA
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參數(shù)描述
XRT75R12ES 功能描述:時鐘合成器/抖動清除器 12CH T3/E3/STS1LIUJA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R12IB 功能描述:外圍驅(qū)動器與原件 - PCI 12CH E3/DS3/STS W/JITTER R3 TECH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R12IB-F 功能描述:外圍驅(qū)動器與原件 - PCI 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R12IB-L 功能描述:LIN 收發(fā)器 Attenuator RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
XRT75VL00 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
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