參數(shù)資料
型號: XRT73R12
廠商: Exar Corporation
英文描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述: 第十二章通道E3/DS3/STS-1線路接口單元
文件頁數(shù): 76/87頁
文件大?。?/td> 436K
代理商: XRT73R12
XRT73R12
REV. P1.0.3
PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
73
T
ABLE
32: XRT73R12 R
EGISTER
MAP
SHOWING
T
RANSMIT
C
ONTROL
R
EGISTERS
(TC_
N
)
T
ABLE
33: T
RANSMIT
C
ONTROL
R
EGISTER
- C
HANNEL
N
A
DDRESS
L
OCATION
= 0
XM
4
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Reserved
Internal
Transmit
Drive Monitor
Insert PRBS
Error
Reserved
TAOS
TxCLKINV
TxLEV
R/W
R/W
R/W
R/W
R/W
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION
7 - 6
Reserved
5
Internal Transmit
Drive Monitor
Enable
R/W
Internal Transmit Drive Monitor Enable - Channel_n:
This READ/WRITE bit-field is used to configure the Transmit Section of
Channel_n to either internally or externally monitor the TTIP_n and
TRING_n output pins for bipolar pulses, in order to determine whether
to declare the Transmit DMO Alarm condition.
If the user configures the Transmit Section to externally monitor the
TTIP_n and TRING_n output pins (for bipolar pulses) then the user
must connect the MTIP_n and MRING_n input pins to their corre-
sponding TTIP_n and TRING_n output pins (via a 270 ohm series
resistor).
If the user configures the Transmit Section to internally monitor the
TTIP_n and TRING_n output pins (for bipolar pulses), the user does
NOT need to conect the MTIP_n and MRING_n input pins. This moni-
toring will be performed internally at the TTIP_n and TRING_n pads.
0 - Configures the Transmit Drive Monitor to externally monitor the
TTIP_n and TRING_n output pins for bipolar pulses.
1 - Configures the Transmit Drive Monitor to internally monitor the
TTIP_n and TRING_n output pins for bipolar pulses.
4
Insert PRBS Error
R/W
Insert PRBS Error - Channel_n:
A "0 to 1" transition within this bit-field causes the PRBS Generator
(within the Transmit Section of Channel_n) to generate a single bit
error within the outbound PRBS pattern-stream.
N
OTES
:
1.
This bit-field is only active if the PRBS Generator and
Receiver have been enabled within the corresponding
Channel.
2.
After writing the "1" into this register, the user must execute a
write operation to clear this particular register bit to "0" in
order to facilitate the next "0 to 1" transition in this bit-field.
3
Reserved
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