參數(shù)資料
型號(hào): XRT73LC00A
廠商: Exar Corporation
英文描述: E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述: E3/DS3/STS-1線路接口單元
文件頁數(shù): 41/53頁
文件大小: 376K
代理商: XRT73LC00A
xr
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.0.0
38
B.
access the Microprocessor Serial Interface and
write a “1” into the RNRZ bit-field in Command
Register CR3.
After these steps are taken, the XRT73LC00A out-
puts Single-Rail data to the Receiving Terminal
Equipment via the RPOS and RCLK1 (or RCLK2)
output pins as illustrated in Figure 27 and Figure 28.
N
OTE
:
The RNEG output pin is internally tied to GND
whenever this feature is enabled.
4.0
DIAGNOSTIC FEATURES OF THE
XRT73LC00A
The XRT73LC00A supports equipment diagnostic ac-
tivities by supporting the following Loop-Back modes
in the chip:
Analog Local Loop-Back
Digital Local Loop-Back
Remote Loop-Back.
4.1
T
HE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
When the XRT73LC00A is configured to operate in
the Analog Local Loop-Back Mode, the XRT73LC00A
ignores any signals that are input to the RTIP and
RRING input pins. The Transmitting Terminal Equip-
ment transmits clock and data into the XRT73LC00A
via the TPDATA, TNDATA and TCLK input pins. This
data is processed through the Transmit Clock Duty
Cycle Adjust PLL and the HDB3/B3ZS Encoder. Fi-
nally, this data outputs to the line via the TTIP and
TRING output pins and is looped back into the AGC/
Receive Equalizer Block. Consequently, this data is
also processed through the Receive Section of the
XRT73LC00A. After this post-loop-back data has
been processed through the Receive Section it out-
puts to the Near-End Receiving Terminal Equipment
via the RPOS, RNEG, RCLK1 and RCLK2 output
pins.
COMMAND REGISTER CR3 (ADDRESS = 0X03)
D4
D3
D2
D1
D0
RNRZ
LOSMUT CLK2DIS
RCLK2INV
RCLK1INV
1
X
X
X
X
F
IGURE
27. T
HE
T
YPICAL
I
NTERFACE
FOR
THE
T
RANSMISSION
OF
D
ATA
IN
A
S
INGLE
-R
AIL
F
ORMAT
F
ROM
THE
R
ECEIVE
S
ECTION
OF
THE
XRT73LC00A
TO
THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
Exar E3/DS3/STS-1 LIU
Receive
Logic
Block
RxPOS
RCLK1, 2
RPOS
RCLK1, 2
F
IGURE
28. T
HE
B
EHAVIOR
OF
THE
RPOS
AND
RCLK1 O
UTPUT
S
IGNALS
W
HILE
THE
XRT73LC00A
IS
T
RANSMIT
-
TING
S
INGLE
-R
AIL
D
ATA
TO
THE
R
ECEIVING
T
ERMINAL
E
QUIPMENT
RCLK1
RPOS
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