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參數(shù)資料
| 型號： | XRT73LC00A |
| 廠商： | Exar Corporation |
| 英文描述： | E3/DS3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | E3/DS3/STS-1線路接口單元 |
| 文件頁數(shù)： | 27/53頁 |
| 文件大?。?/td> | 376K |
| 代理商： | XRT73LC00A |
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the Transmit Logic Block for the occurrence of three
(3) consecutive zeros (“000”). If the B3ZS Encoder
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.0.0
24
The XRT73LC00A Transmit Clock Duty Cycle Adjust
circuit alleviates the need to supply a signal with a
50% duty cycle to the TCLK input pin.
2.3
T
HE
HDB3/B3ZS E
NCODER
B
LOCK
The purpose of the HDB3/B3ZS Encoder Block is to
aid in the Clock Recovery process at the Remote Ter-
minal Equipment by ensuring an upper limit on the
number of consecutive zeros that can exist in the line
signal.
2.3.1
B3ZS Encoding
If the XRT73LC00A is configured to operate in the
DS3 or SONET STS-1 Modes, then the HDB3/B3ZS
Encoder block operates in the B3ZS Mode. When the
Encoder is operating in this mode, it parses through
and searches the Transmit Binary Data Stream from
finds an occurrence of three consecutive zeros, it
substitutes these three “0’s” with either a "00V" or a
"B0V" pattern.
“B” represents a Bipolar pulse that is compliant with
the Alternating Polarity requirements of the AMI (Al-
ternate Mark Inversion) line code and “V” represents
a bipolar Violation (e.g., a bipolar pulse that violates
the Alternating Polarity requirements of the AMI line
code).
The B3ZS Encoder decides whether to substitute
with either a "00V" or a "B0V" pattern to insure that
an odd number of bipolar pulses exist between any
two consecutive violation pulses.
Figure 14 illustrates the B3ZS Encoder at work with
two separate strings of three (or more) consecutive
zeros.
2.3.2
If the XRT73LC00A is configured to operate in the E3
Mode, then the HDB3/B3ZS Encoder block operates
in the HDB3 Mode. When the Encoder is operating in
this mode, it parses through and searches the Trans-
mit Data Stream from the Transmit Logic Block for the
occurrence of four (4) consecutive zeros (“0000”). If
the HDB3 Encoder finds an occurrence of four con-
HDB3 Encoding
secutive zeros, then it substitutes these four “0’s” with
either a “000V” or a “B00V” pattern to insure that an
odd number of bipolar pulses exist between any two
consecutive violation pulses.
Figure 15 illustrates the HDB3 Encoder at work with
two separate strings of four (or more) consecutive ze-
ros.
F
IGURE
14. A
N
E
XAMPLE
OF
B3ZS E
NCODING
TClk
TPOS
SR data
Encoded
PDATA
Encoded
NDATA
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
Line signal
B
V
0
V
0
0
0
F
IGURE
15. A
N
E
XAMPLE
OF
HDB3 E
NCODING
TClk
TPOS
SR data
Encoded
PDATA
Encoded
NDATA
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
Line signal
B
V
0
V
0
0
0
0
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PDF描述 |
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| XRT73LC00AIV | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03A | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03AIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC04A | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC04AIV | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73LC00A_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC00AES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC00AIV | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73LC00AIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI 1-Ch DS3, E3, SONET RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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