參數(shù)資料
型號: XRT73L02M
廠商: Exar Corporation
英文描述: TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述: 雙通道E3/DS3/STS-1線路接口單元
文件頁數(shù): 44/46頁
文件大小: 391K
代理商: XRT73L02M
XRT73L02M
xr
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
42
During the remote loop back mode, if the jitter attenuator is selected in the transmit path, the receive data after
the Clock and Data Recovery Block is looped back to the transmit path and passed through the jitter attenuator
using RxClk as the transmit timing.
N
OTE
:
Input signals on TxClk, TPOS and TNEG are ignored during Remote loop back.
8.3
Transmit All Ones (TAOS) can be set either in Hardware mode by pulling the TAOS_n pins “High” or in Host
mode by setting the TAOS_n control bits to “1” in the Channel control registers. When the TAOS is set, the
Transmit Section generates and transmits a continuous AMI all “1’s” pattern on TTIP_n and TRING_n pins. The
frequency of this “1’s” pattern is determined by TxClk_n.TAOS data path is shown in Figure 29.
TRANSMIT ALL ONES (TAOS):
F
IGURE
27. R
EMOTE
L
OOPBACK
F
IGURE
28. T
RANSMIT
A
LL
O
NES
(TAOS)
TRING
TTIP
RRING
RTIP
RPOS
RNEG
RCLK
TNDATA
TCLK
TPDATA
HDB3/B3ZS
ENCODER
HDB3/B3ZS
DECODER
J
A
J
A
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
1
if enabled
2
if enabled and selected in either Receive or
Transmit path
Tx
Rx
1
1
TRING
TTIP
RRING
RTIP
RPOS
RNEG
RCLK
TNDATA
TCLK
TPDATA
HDB3/B3ZS
ENCODER
HDB3/B3ZS
DECODER
J
A
J
A
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
1
if enabled
2
if enabled and selected in either Receive or
Transmit path
Tx
Rx
TAOS
Transmit All 1'
1
1
相關(guān)PDF資料
PDF描述
XRT73L02MIV TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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