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參數(shù)資料
| 型號： | XRT73L02M |
| 廠商： | Exar Corporation |
| 英文描述： | TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | 雙通道E3/DS3/STS-1線路接口單元 |
| 文件頁數(shù)： | 32/46頁 |
| 文件大?。?/td> | 391K |
| 代理商： | XRT73L02M |
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XRT73L02M
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TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
30
As defined in ITU-T G.775, an LOS condition is also declared between 10 and 255 UI (or E3 bit periods) after
the actual time the LOS condition has occurred. The LOS condition is cleared within 10 to 255 UI after restora-
tion of the incoming line signal. Figure 20 shows the LOS declaring and clearing conditions.
5.0.4.3
When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the E3/
DS3/STS1CLK pin and output this clock on the RxClk_n output. In Single Frequency Mode (SFM), the clock re-
covery locks into the rate clock generated and output this clock on the RxClk_n pins. The data on the RPOS_n
and RNEG_n pins can be forced to zero by pulling the LOSMUT pin “High” (in Hardware Mode) or by setting
the LOSMUT_n bits in the individual channel control register to “1” (in Host Mode).
Muting the Recovered Data with LOS condition:
N
OTE
:
When the LOS condition is cleared, the recovered data is output on RPOS_n and RNEG_n pins.
6.0
JITTER:
There are three fundamental parameters that describe circuit performance relative to jitter:
Jitter Tolerance (Receiver)
Jitter Transfer (Receiver/Transmitter)
Jitter Generation
6.0.1
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the
presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the jit-
ter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error rate
(BER). To measure the jitter tolerance as shown in Figure 21, jitter is introduced by the sinusoidal modulation of
the serial data bit sequence.
J
ITTER
T
OLERANCE
- R
ECEIVER
:
F
IGURE
20. L
OSS
OF
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775.
Actual Occurrence
of LOS Condition
Line Signal
is Restored
Time Range for
LOS Declaration
Time Range for
LOS Clearance
G.775
Compliance
G.775
Compliance
0 UI
10 UI
0 UI
10 UI
255 UI
255 UI
RTIP/
RRing
RLOS Output Pin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73L02MIV | TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02 | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| XRT73L03A | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03AIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03B | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L02MES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73L02MIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73L02MIVTR-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73L03 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT |
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