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參數(shù)資料
| 型號(hào)： | XRT73L02M |
| 廠商： | Exar Corporation |
| 英文描述： | TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | 雙通道E3/DS3/STS-1線路接口單元 |
| 文件頁(yè)數(shù)： | 2/46頁(yè) |
| 文件大?。?/td> | 391K |
| 代理商： | XRT73L02M |
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XRT73L02M
xr
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
2
TRANSMIT INTERFACE CHARACTERISTICS
Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
to the line
Integrated Pulse Shaping Circuit.
Built-in B3ZS/HDB3 Encoder (which can be dis-
abled).
Accepts Transmit Clock with duty cycle of 30%-
70%.
Generates pulses that comply with the ITU-T G.703
pulse template for E3 applications.
Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499
-CORE
and ANSI T1.102_1993.
Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253-
CORE.
Transmitter can be turned off in order to support
redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
Integrated Adaptive Receive Equalization for opti-
mal Clock and Data Recovery.
Declares and Clears the LOS defect per ITU-T
G.775 requirements for E3 and DS3 applications.
Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications.
Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications.
Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms.
Built-in B3ZS/HDB3 Decoder (which can be dis-
abled).
Recovered Data can be muted while the LOS Con-
dition is declared.
Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment.
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT 73L02M
HOST/HW
STS-1/DS3
E3
REQEN
RTIP
RRING
SR/DR
LLB
XRT75L03
RLB
RLOS
TPOS
TNEG
TxClk
TAOS
TxLEV
TxON
Note: Serial Processor Interface input pins are shared by in "Host" Mode and redefined in the "Hardware" Mode.
Device
Monitor
MTIP
MRING
DMO
Timing
Control
TTIP
TRING
Tx
Pulse
Shaping
HDB3/
B3ZS
Encoder
RLOL
RxON
RxClkINV
RxClk
RPOS
RNEG/
LCV
Tx
Control
MUX
Line
Driver
Invert
Remote
LoopBack
HDB3/
B3ZS
Decoder
MUX
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer
Serial
Processor
Interface
Local
LoopBack
Clock & Data
Recovery
Clock
Synthesizer
E3Clk,DS3Clk,
STS-1Clk
RESET
CS
SClk
INT
SDO
SDI
CLK_OUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73L02MIV | TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02 | 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元) |
| XRT73L03A | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03AIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L03B | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L02MES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73L02MIV | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L02MIV-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73L02MIVTR-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73L03 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT |
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