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XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
REV. P1.1.2
III
R
X
E3 LAPD C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
18) ............................................................................. 88
R
X
E3 LAPD S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
19) ................................................................................ 88
R
X
E3 NR B
YTE
R
EGISTER
(A
DDRESS
= 0
X
1A) ........................................................................................ 89
R
X
E3 GC B
YTE
R
EGISTER
(A
DDRESS
= 0
X
1B) ....................................................................................... 89
R
X
E3 TTB-0 R
EGISTER
(A
DDRESS
= 0
X
1C) ............................................................................................ 90
R
X
E3 TTB-1 R
EGISTER
(A
DDRESS
= 0
X
1D) ............................................................................................ 90
R
X
E3 TTB-2 R
EGISTER
(A
DDRESS
= 0
X
1E) ............................................................................................ 90
R
X
E3 TTB-3 R
EGISTER
(A
DDRESS
= 0
X
1F) ............................................................................................ 91
R
X
E3 TTB-4 R
EGISTER
(A
DDRESS
= 0
X
20) ............................................................................................ 91
R
X
E3 TTB-5 R
EGISTER
(A
DDRESS
= 0
X
21) ............................................................................................ 91
R
X
E3 TTB-6 R
EGISTER
(A
DDRESS
= 0
X
22) ............................................................................................ 91
R
X
E3 TTB-7 R
EGISTER
(A
DDRESS
= 0
X
23) ............................................................................................ 92
R
X
E3 TTB-8 R
EGISTER
(A
DDRESS
= 0
X
24) ............................................................................................ 92
R
X
E3 TTB-9 R
EGISTER
(A
DDRESS
= 0
X
25) ............................................................................................ 92
R
X
E3 TTB-10 R
EGISTER
(A
DDRESS
= 0
X
26) .......................................................................................... 93
R
X
E3 TTB-11 R
EGISTER
(A
DDRESS
= 0
X
27) .......................................................................................... 93
R
X
E3 TTB-12 R
EGISTER
(A
DDRESS
= 0
X
28) .......................................................................................... 93
R
X
E3 TTB-13 R
EGISTER
(A
DDRESS
= 0
X
29 ........................................................................................... 93
R
X
E3 TTB-14 R
EGISTER
(A
DDRESS
= 0
X
2A) .......................................................................................... 94
R
X
E3 TTB-15 R
EGISTER
(A
DDRESS
= 0
X
2B) .......................................................................................... 94
R
X
E3
SSM
R
EGISTER
(A
DDRESS
= 0
X
2B) ................................................................................................ 94
2.4.4 Receive E3 Framer Configuration Registers (ITU-T G.751) ................................................................... 95
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
- 1 G.751 (A
DDRESS
= 0
X
10) ............................................. 95
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
11) ........................................................ 95
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 1 (A
DDRESS
= 0
X
12) ................................................................... 96
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) ................................................................... 97
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) ................................................................... 97
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................... 98
R
X
E3 LAPD C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
18) ............................................................................. 99
R
X
E3 LAPD S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
19) ................................................................................ 99
R
X
E3 S
ERVICE
B
IT
R
EGISTER
(A
DDRESS
= 0
X
1A) ................................................................................. 100
2.4.5 Transmit DS3 Configuration Registers .................................................................................................. 100
T
RANSMIT
DS3 C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
30) ............................................................. 101
T
RANSMIT
DS3 FEAC C
ONFIGURATION
& S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
31) .................................. 102
T
X
DS3 FEAC R
EGIS
T
ER
(A
DDRESS
= 0
X
32) ........................................................................................ 103
T
X
DS3 LAPD C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
33) ............................................................... 103
T
X
DS3 LAPD S
TATUS
AND
I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34) ................................................... 104
T
X
DS3 M-B
IT
M
ASK
R
EGISTER
(A
DDRESS
= 0
X
35) ............................................................................... 104
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
- 1 (A
DDRESS
= 0
X
36) ........................................................................... 105
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
- 2 (A
DDRESS
= 0
X
37) ........................................................................... 106
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
- 3 (A
DDRESS
= 0
X
38) ........................................................................... 106
T
X
DS3 F-B
IT
M
ASK
R
EGISTER
- 4 (A
DDRESS
= 0
X
39) ........................................................................... 106
2.4.6 Transmit E3 (ITU-T G.832) Configuration Registers ............................................................................. 106
T
X
E3 C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
30) ............................................................................ 107
T
X
E3 LAPD C
ONFIGURATION
R
EGISTER
(A
DDRESS
= 0
X
33) ................................................................. 108
T
X
E3 LAPD S
TATUS
AND
I
NTERRUPT
R
EGISTER
(A
DDRESS
= 0
X
34) ...................................................... 108
T
X
E3 GC B
YTE
R
EGISTER
(A
DDRESS
= 0
X
35) ...................................................................................... 109
T
X
E3 MA B
YTE
R
EGISTER
(A
DDRESS
= 0
X
36) ...................................................................................... 110
T
X
E3 MA B
YTE
R
EGISTER
(A
DDRESS
= 0
X
36) ...................................................................................... 110
T
X
E3 NR B
YTE
R
EGISTER
(A
DDRESS
= 0
X
37) ...................................................................................... 110
T
X
E3 TTB-0 R
EGISTER
(A
DDRESS
= 0
X
38) ........................................................................................... 111
T
X
E3 TTB-1 R
EGISTER
(A
DDRESS
= 0
X
39) ........................................................................................... 111
T
X
E3 TTB-2 R
EGISTER
(A
DDRESS
= 0
X
3A) .......................................................................................... 111
T
X
E3 TTB-3 R
EGISTER
(A
DDRESS
= 0
X
3B) .......................................................................................... 112
T
X
E3 TTB-4 R
EGISTER
(A
DDRESS
= 0
X
3C) .......................................................................................... 112