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XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
REV. P1.1.3
XIX
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
2 (A
DDRESS
= 0
X
11) ........................................................ 447
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) ................................................................. 447
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................. 448
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) ................................................................. 448
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................. 448
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) ................................................................. 449
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................. 449
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
1 (A
DDRESS
= 0
X
10) ........................................................ 450
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) ................................................................. 450
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................. 450
R
X
E3 LAPD C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
18) ........................................................................... 451
R
X
E3 LAPD C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
18) ........................................................................... 451
7.0 diagnostic operation of the xrt72L52 framer ic .............................................................................. 452
Figure 213. Illustration of the Framer Local Loop-back path, within the XRT72L52 DS3/E3 Framer IC 452
8.0 High Speed HDLC Controller Mode of Operation ........................................................................... 454
8.1 C
ONFIGURING
THE
C
HANNEL
TO
OPERATE
IN
THE
H
IGH
S
PEED
HDLC C
ONTROLLER
M
ODE
................................. 454
T
ABLE
93: A
DDRESS
L
OCATIONS
OF
EACH
OF
THE
HDLC CONTROL R
EGISTERS
WITHIN
THE
XRT72L52 D
E
-
VICE
. .................................................................................................................................................... 454
HDLC C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
82) ..................................................................................... 454
8.2 O
PERATING
THE
H
IGH
S
PEED
HDLC C
ONTROLLER
............................................................................................ 454
8.2.1 Operating the Transmit HDLC Controller Block .................................................................................... 455
T
ABLE
94: D
ESCRIPTION
OF
E
ACH
OF
THE
T
RANSMIT
HDLC C
ONTROLLER
P
INS
.................................... 456
Figure 214. A Simple Illustration of an Outbound HDLC Frame, as assembled by the Transmit HDLC Con-
troller, when CRC-32 is selected. ........................................................................................................ 457
Figure 215. A Simple Illustration of an Outbound HDLC Frame, as assembled by the Transmit HDLC Con-
troller, when CRC-16 is selected. ........................................................................................................ 458
8.2.2 Operating the Receive HDLC Controller Block ..................................................................................... 458
T
ABLE
95: D
ESCRIPTION
OF
E
ACH
OF
THE
R
ECEIVE
HDLC C
ONTROLLER
P
INS
...................................... 459
ORDERING INFORMATION ........................................................................................ 460
PACKAGE DIMENSIONS ............................................................................................ 460
R
EVISION
H
ISTORY
................................................................................................................................ 461