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參數(shù)資料
| 型號： | XRT7295AT |
| 廠商： | Exar Corporation |
| 英文描述： | DS3/Sonet STS-1 Integrated Line Receiver |
| 中文描述： | DS3/Sonet STS - 1的集成線路接收器 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 1072K |
| 代理商： | XRT7295AT |
XRT7295AT
11
Rev.1.20
JITTER ACCOMMODATION
Under all allowable operating conditions, the jitter
accommodation of the XRT7295AT device exceeds all
system
requirements
for
(BER<1E
-9
). The typical (V
DD
= 5V, T = 25
°
C, DSX-3
nominal signal level) jitter accommodation for the
XRT7295AT is shown in
Figure 10.
error-free
operation
FALSE-LOCK IMMUNITY
False-lock is defined as the condition where a PLL
recoveredclock obtains stable phase-lockat a frequency
not equal to the incoming data rate. The XRT7295AT
device
uses
a
combination
architecture to prevent false-lock. An on-chip frequency
comparatorcontinuouslycomparestheEXCLKreference
to the PLL clock. If the frequency difference between the
EXCLK and PLL clock exceeds approximately
correction circuitry forces re-acquisition of the proper
frequency and phase.
frequency/phase-lock
±
0.5%,
ACQUISITION TIME
If a valid input signal is assumed to be already present at
R
IN
, the maximumtime betweentheapplicationof device
power and error-free operation is 20ms. If power has
alreadybeenapplied,theintervalbetweentheapplication
of valid data (or the action of valid data following a loss of
signal) and error-free operation is 4ms.
LOSS-OF-LOCK DETECTION
Asstatedabove,thePLLacquisitionaidcircuitrymonitors
thePLLclockfrequencyrelativetotheEXCLKfrequency.
TheRLOLalarmisactivatedifthedifferencebetweenthe
PLL
clock
and
the
EXCLK
approximately
±
0.5%.
frequency
exceeds
Thiswillnotoccuruntilatleast250bitperiodsafterlossof
input data.
Figure 9. Typical PLL Jitter Transfer
Characteristic
1
0
-5
-4
-3
-2
-1
100
500 1K
5K 10K
50K100K
500K
PEAK = 0.05dB
f3dB = 205kHz
Frequency (Hz)
M
1
10
100
1K
10K
100K
1000K
40
10
1.0
0.1
XRT7295AT Typical
PUB 54014
G.824
TR-TSY-000499
Category 1
TR-TSY-000499
Category 2
5k
10
5
1
0.5
0.4
10k
60k
300k
1M
XRT7295AT Typical
Sinewave Jitter Frequency (Hz)
Figure 10. Input Jitter Tolerance at DSX-3 Level
Jitter
Frequency
(Hz)
Jitter
Amplitude
(U.I.)
P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT7295ATIW | DS3/Sonet STS-1 Integrated Line Receiver |
| XRT7295 | () |
| XRT7296 | INTEGRATED LINE TRANSMITTER |
| XRT7296IP | INTEGRATED LINE TRANSMITTER |
| XRT7296IW | INTEGRATED LINE TRANSMITTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT7295AT_10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3 SONET STS1 Integrated Line Receiver |
| XRT7295ATIW | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7295ATIW-F | 功能描述:外圍驅(qū)動器與原件 - PCI -.5V--6.5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7295ATIW-F | 制造商:Exar Corporation 功能描述:T3/E3 LIU IC |
| XRT7295ATIWTR | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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