參數(shù)資料
型號(hào)： XRT4000
廠商： Exar Corporation
英文描述： Universal Multiprotocol Serial Interface
中文描述： 通用多協(xié)議串行接口
文件頁數(shù)： 6/46頁
文件大?。?/td> 396K
代理商： XRT4000
XRT4000
Rev. 1.00
- 6 -
PIN DESCRIPTION
Pin
#
1
2
3
4
5
6
Symbol
DTE
Mode
DCE
Mode
Type
Function
VDD
GND
M0
M1
M2
EN_FLTR
Digital VDD for Receiver 1
- Connect to +5V
Digital GND for Receiver 1
Mode Control
- Mode Select Input 0; Internal 20K
pull-up
Mode Control
- Mode Select Input 1; Internal 20K
pull-up
Mode Control
- Mode Select Input 2; Internal 20K
pull-up
Enable Glitch Filter
on Receiver 4, 5, 6, 7, 8 inputs.
Internal 20K
pull-down
Enable
input termination for Receiver 1, 2, 3 in V.11 Mode.
Internal 20K
pull-down
Mode Control Input Latch Enable
-
Logic 0
: Changes on
M0, 1, 2, EN_FLTR, and EN_TERM pins cause mode
changes (input latches in transparent state).
Logic 1
: Changes on these input pins do not cause mode
changes (input latches in latched state). Internal 20K
pull-
down
Digital VSS
for Transmitter 4, 5, 6. Connect to -6V
Analog VSS
for bias generation Connect to -6V
Digital GND
for Transmitter 7, 8
Internal Clock Generated
- 500kHz
Transmitter 4
- Digital Data Input from equipment
Digital VDD
for Transmitter 4, 5, 6; Connect to +5V
Transmitter 4
- Positive Data Differential Output to line
Transmitter 4
- Negative Data Differential Output to line
Transmitter 5
- Negative Data Differential Output to line
Transmitter
5
- Positive Data Differential Output to line
Digital GND
for Transmitter 4, 5, 6
Transmitter 5
- Digital Data Input from equipment
Transmitter 8
- Digital Data Input from equipment
Loopback Enable
- Active low;
Logic 0
: Loopback
enabled.
Logic 1
: Loopback disabled. Internal 20K
pull-up
Transmitter 8
- Single Ended Data Output to line
Digital VSS
for Transmitter 7, 8; Connect to -6V
Digital VDD
for Transmitter 7, 8; Connect to +5V
Output Enable
for Receiver 5, 8; Internal 20K
pull-down
Register Control
-
Logic 1
: TX5D, TX8D signal values will
be latched on the positive edge of REG_CLK,
Logic 0:
The
Register flip-flop is bypassed therefore REG_CLK has no
effect on these signals. Internal 20K
pull-down
Analog VSS
for Receiver 4, 5, 6; Connect to -6V
Analog VDD
for Receiver 4, 5, 6; Connect to +5V
Analog VDD
for Receiver 7, 8; Connect to +5V
Receiver 8
- Digital Data Output to equipment
Analog GND
for Receiver 7, 8
Receiver 8
- Single Ended Data Input from line
Analog VSS
for Receiver 7, 8; Connect to -6V
I
I
I
I
7
EN_TERM
I
8
LATCH*
I
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VSS
VSS
GND
CLKFS
TX4D
VDD
TX4B
TX4A
TX5A
TX5B
GND
TX5D
TX8D
LP*
O
I
D_RTS
D_CTS
RTSB
RTSA
DTRA
DTRB
CTSB
CTSA
DSRA
DSRB
O
O
O
O
D_DTR
D_RL
D_DSR
D_RI
I
I
I
23
24
25
26
27
TX8O
VSS
VDD
EN_OUT*
REG
RLA
RIA
O
I
I
28
29
30
31
32
33
34
VSS
VDD
VDD
RX8D
GND
RX8I
VSS
D_RI
D_RL
O
RIA
RLA
I
Note:
An asterisk (*) following a pin symbol indicates that the pin is active low.
Names begining with D_ are digital signals.
Names ending with B and A are the positive and negative polarities of differential signals respectively.
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