
XRT4000
Rev. 1.00
- 17 -
CONTROL Block
The CONTROL block contains the configuration
and bias generation circuitry required by
RTMOD1, RTMOD2, and RTMOD3. It includes
TTL to CMOS level shifters for the control signal
inputs which have either an internal 20 k
pull-
up or pull-down resistor as shown in Figure 5
and as described in the pin description. This
block also includes a reference voltage source,
bias voltage and current generators, and a slew
rate control circuit that is used in the V.10 and
V.28
modes.
The
configuration is done by three control pins called
M0, M1 and M2. The logic levels present on
these three inputs are internally latched during a
positive transition of the LATCH* signal. The
functions of the eight possible combinations of
M0, M1 and M2 are described in Tables 1 and 2.
physical
interface
Power Requirements
Table 3, which contains the maximum and
minimum peak supply currents for each of the 3
supply voltages, provides the information
necessary for determining a system power
budget. Notice that maximum current is
required in the V.11 mode when TX1, TX2, and
TX3 are terminated with 100
. Minimum current
consumption
occurs
transmitters are terminated and the device is not
in the V.35 mode.
when
none
of
the
Receiver and Transmitter Specifications
Tables 4 and 5, which are for the XRT4000
receiver and transmitter sections respectively,
summarize the electrical requirements for V.35,
V.11, V.10, and RS232 interfaces. These tables
provide virtually all of the electrical information
necessary to describe these 4 interfaces in a
concise form.