參數(shù)資料
型號: XRP7714ILB-0X14-F
廠商: Exar Corporation
文件頁數(shù): 19/29頁
文件大?。?/td> 1009K
描述: IC REG 5OUT BCK/LINEAR 40TQFN
標(biāo)準(zhǔn)包裝: 490
系列: PowerXR
拓?fù)洌?/td> 降壓(降壓)同步(4),線性(LDO)(1)
功能: 任何功能
輸出數(shù): 5
頻率 - 開關(guān): 1.5MHz
電壓/電流 - 輸出 1: 控制器
電壓/電流 - 輸出 2: 控制器
電壓/電流 - 輸出 3: 控制器
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 4.75 V ~ 25 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-TQFN(6x6)
包裝: 托盤
其它名稱: 1016-1700
X
X
R
R
P
P
7
7
7
7
1
1
4
4
 
 
Q
Q
u
u
a
a
d
d
 
 
C
C
h
h
a
a
n
n
n
n
e
e
l
l
 
 
D
D
i
i
g
g
i
i
t
t
a
a
l
l
 
 
P
P
W
W
M
M
 
 
S
S
t
t
e
e
p
p
 
 
D
D
o
o
w
w
n
n
 
 
C
C
o
o
n
n
t
t
r
r
o
o
l
l
l
l
e
e
r
r
 
 
 
?2011 Exar Corporation
19/29
Rev. 1.1.6
SOFT-STOP
The SET_PD_FALL_CHx register is a 16 bit register. This register specifies the soft-stop delay and
ramp (fall-time) characteristics for when the chip receives a channel disable indication from the
Host to shutdown the channel.
Bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the
channel; where each bit represents 250祍 steps. Bits [9:0] specify the fall time of the channel;
these 10 bits define the number of microseconds for each 50mV increment to reach the discharge
threshold.
DELAY
Fall Time
Bit [10:15]
Bit [0:9]
Vout
Enable
Signal
PD_DELAY_CHx
REGISTER
 
Fig. 25: Channel Soft-Stop Sequence
POWER GOOD FLAG
The XRP7714 allows the user to set the upper and lower bound for a power good signal per
channel.     The     SET_PWRG_TARG_MAX_CHx     register     sets     the     upper     bound,     the
SET_PWRG_TARG_MIN_CHx register sets the lower bound. Each register has a 20mV LSB
resolution. When the output voltage is within bounds the power good signal is asserted high.
Typically the upper bound should be lower than the over-voltage threshold. In addition, the power
good signal can be delayed by a programmable amount set in the SET_PWRGD_DLY_CHx register.
The power good delay is only set after the soft-start period is finished. If the channel has a pre-
charged condition that falls into the power good region, a power good flag is not set until the soft-
start is finished.
PWM SWITCHING FREQUENCY
The PWM switching frequency is set by choosing the corresponding oscillator frequency and clock
divider ratio in the SET_SW_FREQUENCY register. Bits [6:4] set the oscillator frequency and bits
[2:0] set the clock divider. The tables below summarize the available Main Oscillator and PWM
switching frequency settings in the XRP7714.
Main Oscillator Frequency
SET_SW_FREQUENCY[6:4]
000
001
010
011
100
101
110
111
M  in
ill    r Fr
n
48MHz    44.8MHz   41.6MHz   38.4MHz   35.2MHz    32MHz    28.8Mhz   25.6MHz
T
20.8ns     22.3ns
24ns
26ns
28.4ns    31.25ns    34.7ns
39ns
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