參數(shù)資料
型號(hào)： XR20M1172L32-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 8/55頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR20M1172 32QFN
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR20M1172
主要屬性： 2 通道
次要屬性： I²C & SPI 接口
已供物品： 板
其它名稱： 1016-1625
XR20M1172L32-0B-EB-ND
XR20M1172
16
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.2.0
2.7.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.7.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. The Non-FIFO Mode is
enabled by default for 16450 compatibility. For normal operation, the FIFO Mode must be enabled.
2.7.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
FIGURE 13. TRANSMITTER OPERATION IN NON-FIFO MODE
FIGURE 14. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X or 8X or 4X
Clock
( DLD[5:4] )
Transm it Data Shift Register
(TSR)
Transm it
Data Byte
TH R Interrupt (ISR bit-1) falls
below the program m ed Trigger
Level and then w hen becom es
em pty. FIFO is Enabled by FC R
bit-0=1
Transm it
FIFO
16X or 8X or 4X Clock
( DLD[5:4] )
Auto C TS Flow Control (CTS# pin)
Auto Software Flow C ontrol
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.)
TXFIFO 1
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