參數(shù)資料
型號: XR20M1172L32-0B-EB
廠商: Exar Corporation
文件頁數(shù): 6/55頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR20M1172 32QFN
標準包裝: 1
主要目的: 接口,UART
嵌入式:
已用 IC / 零件: XR20M1172
主要屬性: 2 通道
次要屬性: I²C & SPI 接口
已供物品:
其它名稱: 1016-1625
XR20M1172L32-0B-EB-ND
XR20M1172
14
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.2.0
When using 4X sampling mode, the bit time will have a jitter of ± 1/8 whenever DLD is non-zero, odd and not a
multiple of 4.
When using a non-standard data rate crystal or external clock, the divisor value can be
calculated with the following equation(s):
The closest divisor that is obtainable in the M1172 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode,
DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode,
DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode,
DLD[5:4] = ’10’
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
FIGURE 12. BAUD RATE GENERATOR
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL, DLM and DLD
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X or 8X or 4X
Sampling
Rate Clock
to Transmitter
and Receiver
Fractional Baud
Rate Generator
Logic
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