REV. 1.1.0 I2C/SPI UART WITH 64-BYTE FIFO 2.8 Receiver The receiver section contains an 8-bit Receive Shift Register" />
參數(shù)資料
型號： XR20M1170L24-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 7/56頁
文件大小： 0K
描述： EVAL BOARD FOR XR20M1170 24QFN
標準包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR20M1170
次要屬性： I²C & SPI 接口
已供物品： 板
其它名稱： 1016-1621
XR20M1170L24-0B-EB-ND
XR20M1170
15
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
2.8
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks
(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is
sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same
manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4
word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR
interrupt is enabled by IER bit-0.
2.8.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 15. RECEIVER OPERATION IN NON-FIFO MODE
R eceive D ata Shift
R egister (R SR)
Receive
D ata Byte
and Errors
R H R Interrupt (ISR bit-2)
Receive Data
H olding R egister
(R H R)
R XFIFO 1
16X or 8X or 4X C lock
( D LD[5:4] )
R eceive Data Characters
D ata Bit
Validation
Error
Tags in
LSR bits
4:2
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