REV. 1.1.0 I2C/SPI UART WITH 64-BYTE FIFO EFCR[6]: Reserved EFCR[5]: Auto RS-485 Polarity Inversion This bit changes the polarity " />
參數(shù)資料
型號(hào)： XR20M1170L24-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 31/56頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR XR20M1170 24QFN
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR20M1170
次要屬性： I²C & SPI 接口
已供物品： 板
其它名稱： 1016-1621
XR20M1170L24-0B-EB-ND
XR20M1170
37
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
EFCR[6]: Reserved
EFCR[5]: Auto RS-485 Polarity Inversion
This bit changes the polarity of the Auto RS-485 Half-Duplex Direction Control output (RTS#). This bit will only
affect the behavior of the RTS# output if EFCR[4] = 1. See “Section 2.14, Auto RS485 Half-duplex Control”
on page 18 for complete details.
Logic 0 = RTS# output is LOW when transmitting and HIGH when receiving.
Logic 1 = RTS# output is HIGH when transmitting and LOW when receiving.
EFCR[4]: Auto RS-485 Enable
This bit enables the RTS# output as the Auto RS-485 Half-Duplex Direction Control output. See “Section
Logic 0 = RTS# output can be used for Auto RTS Hardware Flow Control or as a general purpose output.
Logic 1 = RTS# output enabled as the Auto RS-485 Half-Duplex Direction Control output.
EFCR[3]: Reserved
EFCR[2]: Transmitter Disable
UART does not send serial data out on the TX output pin, but the TX FIFO will continue to receive data from
CPU until full. Any data in the TSR will be sent out before the trasnmitter goes into disable state.
Logic 0 = Transmitter is enabled
Logic 1 = Transmitter is disabled
EFCR[1] = Receiver Disable
UART will stop receiving data immediately once this bit is set to a Logic 1. Any data that is being received in
the TSR will be received correctly and sent to the RX FIFO.
Logic 0 = Receiver is enabled
Logic 1 = Receiver is disabled
EFCR[0]: 9-bit or Multidrop Mode Enable
This bit enables 9-bit or Multidrop mode. See “Section 2.14, Auto RS485 Half-duplex Control” on page 18
for complete details.
Logic 0 = Normal 8-bit mode
Logic 1 = Enable 9-bit or Multidrop mode
4.20
Baud Rate Generator Registers (DLL, DLM and DLD[3:0]) - Read/Write
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. SEE”PROGRAMMABLE BAUD RATE GENERATOR WITH
DLD[5:4]: Sampling Rate Select
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參數(shù)描述
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XR20M1170L28-0B-EB 功能描述:界面開發(fā)工具 Supports M1170 28pin QFN, SPI Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
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XR20M1172G28-0A-EB 功能描述:UART 接口集成電路 Supports M1172 28 ld TSSOP, I2C Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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