TABLE 16: UART RESET STATES
DLM, DLL
DLM = 0x00 and DLL = 0x01[1]
DLD
Bits 7-0 = 0x00
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x1D
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF[1]
TCR
Bits 7-0 = 0x0F
TLR
Bits 7-0 = 0x00
TXLVL
Bits 7-0 = 0x40
RXLVL
Bits 7-0 = 0x00
IODir
Bits 7-0 = 0x00
IOState
Bits 7-0 = 0x00
IOIntEna
Bits 7-0 = 0x00
IOCont
Bits 7-0 = 0x00
EFCR
Bits 7-0 = 0x00
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00[1]
XON2
Bits 7-0 = 0x00[1]
XOFF1
Bits 7-0 = 0x00[1]
XOFF2
Bits 7-0 = 0x00[1]
I/O SIGNALS
TX
HIGH
RTS#
HIGH
DTR#
HIGH
IRQ#
HIGH
XR20M1170
40
I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.1.0
NOTE: [1] Only resets to these values during a power up. They do not reset when the RESET# pin is asserted or during
software reset IOCont[3] = 1.
REGISTERS
RESET STATE