REV. 1.0.3 TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER EMSR[6]: LSR Interrupt Mode " />
參數(shù)資料
型號: XR19L402IL48-F
廠商: Exar Corporation
文件頁數(shù): 29/49頁
文件大?。?/td> 0K
描述: IC UART/TXRX RS485 48QFN
標準包裝: 260
特點: *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 托盤
XR19L402
35
REV. 1.0.3
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
EMSR[6]: LSR Interrupt Mode
Logic 0 = LSR Interrupt Delayed (for 16C2550 compatibility, default). LSR bits 2, 3, and 4 will generate an
interrupt when the character with the error is in the RHR.
Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
EMSR[7]: 16X Sampling Rate Mode
Logic 0 = 8X Sampling Rate.
Logic 1 = 16X Sampling Rate (default).
4.12
FIFO Level Register (FLVL) - Read-Only
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this is
not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 12 for details.
4.13
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD/16 to achieve the fractional baud rate divisor. DLD must be enabled
via EFR bit-4 before it can be accessed. SEE”PROGRAMMABLE BAUD RATE GENERATOR WITH
4.14
Device Identification Register (DVID) - Read Only
This register contains the device ID (0x0A). Prior to reading this register, DLL and DLM should be set to 0x00
(DLD = 0xXX).
4.15
Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00 (DLD = 0xXX).
4.16
Trigger Level Register (TRG) - Write-Only
User Programmable Transmit/Receive Trigger Level Register. If both the TX and RX trigger levels are used,
the TX trigger levels must be set before the RX trigger levels.
1
0
1
0
1
0
1
±40
±44
±48
±52
1
0
1
0
1
0
1
±12
±20
±28
±36
TABLE 13: XON/XOFF HYSTERESIS
EMSR
BIT-5
EMSR
BIT-4
FCTR
BIT-1
FCTR
BIT-0
XON/XOFF
HYSTERESIS
(CHARACTERS)
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