REV. 1.0.3 TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER LCR[6]: Transmit Break Enable When enabled, the Break control bit cau" />
參數(shù)資料
型號: XR19L402IL48-F
廠商: Exar Corporation
文件頁數(shù): 25/49頁
文件大?。?/td> 0K
描述: IC UART/TXRX RS485 48QFN
標(biāo)準(zhǔn)包裝: 260
特點: *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 托盤
XR19L402
31
REV. 1.0.3
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL, DLM and DLD) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
4.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
DTR# is not available as an output pin on the L402, but it is available for use during internal loopback mode. In
internal loopback mode, this bit is used to write the state of the DSR# interface signal.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Output
RTS# is not available as an output pin on the L402, but it is available for use during internal loopback mode. In
internal loopback mode, this bit is used to write the state of the CTS# interface signal. If half-duplex mode is
enabled via the Half/Full# pin or in is a modem control output and may be used for automatic hardware flow
control by enabled by EFR bit-6. The RTS# pin can also be used for Auto RS485 Half-Duplex direction control
enabled by FCTR bit-3. If the modem interface is not used, this output may be used as a general purpose
output.
Logic 0 = Force RTS# HIGH (default).
Logic 1 = Force RTS# LOW.
MCR[2]: Reserved
OP1# is not available as an output pin on the L402. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: OP2# Output / INT Output Enable
This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output. Also, if 16/68# pin selects Motorola bus interface mode, this bit must be set to
logic 0.
Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).
Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 12.
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