REV. 1.0.3 SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER 2.7 Crystal or External Clock Input The L400 includes" />
參數(shù)資料
型號(hào)： XR19L400IL40TR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 46/46頁(yè)
文件大?。?/td> 0K
描述： IC UART/TXRX RS485 40QFN
標(biāo)準(zhǔn)包裝： 3,000
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V，5V
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-QFN 裸露焊盤（6x6）
包裝： 帶卷 (TR)
XR19L400
9
REV. 1.0.3
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
2.7
Crystal or External Clock Input
The L400 includes an on-chip oscillator (XTAL1 and XTAL2) to generate a clock when a crystal is connected
between the XTAL1 and XTAL2 pins of the device. Alternatively, an external clock can be supplied through the
XTAL1 pin. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock input and XTAL2 pin is the bufferred output which can be used as a clock signal for
other devices in the system. Please note that the input XTAL1 is not 5V tolerant and therefore, the maximum
voltage at the pin should be 3.3V when an external clock is supplied. For programming details, see
“Programmable Baud Rate Generator.”
FIGURE 5. TYPICAL CRYSTAL CONNECTIONS
C1
22-47pF
C2
22-47pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120
(Optional)
R2
500K - 1M
XTAL1
XTAL2
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. When VCC = 5V, the on-chip oscillator
can operate with a crystal whose frequency is not greater than 24 MHz. On the other hand, the L400 can
accept an external clock of up to 64 MHz at XTAL1 pin which results in a maximum data rate of 8 Mbps. For
further reading on the oscillator circuit please see DAN108 on EXAR’s web site at http://www.exar.com.
2.8
Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X or 8X sampling clock of the serial data rate. The sampling clock is used by the transmitter for data
bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the value
of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during
initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and
the DLD register provides the fractional part of the dvisior. Only the four lower bits of the DLD are implemented
and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming
the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data
rate. Table 3 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate.
If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 3. At
8X sampling rate, these data rates would double. Also, when using 8X sampling mode, please note that the bit-
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