REV. 1.0.3 SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER ] TABLE
參數(shù)資料
型號(hào)： XR19L400IL40TR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 18/46頁(yè)
文件大?。?/td> 0K
描述： IC UART/TXRX RS485 40QFN
標(biāo)準(zhǔn)包裝： 3,000
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V，5V
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 40-QFN 裸露焊盤(pán)（6x6）
包裝： 帶卷 (TR)
XR19L400
25
REV. 1.0.3
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
]
TABLE 7: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Receive Data Time-out)
3
0
1
0
RXRDY (Received Data Ready)
4
0
1
0
TXRDY (Transmit Ready)
5
0
MSR (Modem Status Register)
6
0
1
0
RXRDY (Received Xoff character)
-
0
1
None (default) or Wake-up Indicator
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition) or the device has come out of sleep mode.
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 7).
ISR[4]: Xoff Character Interrupt Status (requires EFR bit-4=1)
This bit is enabled when IER[5] = 1. ISR bit-4 indicates that the receiver detected a data match of the Xoff
character(s).
ISR[5]: Reserved
For normal operation, this bit should remain a logic 0.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, and set the transmit/receive FIFO trigger levels.
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR19L402 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
XR19L402_09 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
XR19L402IL48 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
XR19L402IL48-0B-EB 功能描述:界面開(kāi)發(fā)工具 Supports L402 48 pin QFN, PCI Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
XR19L402IL48-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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