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參數(shù)資料
型號: XR19L220IL40-0B-EB
廠商: Exar Corporation
文件頁數(shù): 34/43頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR19L202 40QFN
標準包裝: 1
系列: *
XR19L220
4
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
NOTE: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. For CMOS/TTL Voltage levels, ’LOW’
indicates a voltage in the range 0V to VIL and ’HIGH" indicates a voltage in the range VIH to VCC. For RS-232
input voltage levels, ’LOW’ is any voltage < -3V and ’HIGH’ is any voltage > 3V. For RS-232 output voltage levels,
’LOW’ is any voltage < -5V and ’HIGH’ is any voltage > 5V.
CD
39
I
UART Carrier-Detect or general purpose input. This input has an internal pull-down resistor
and can be left unconnected when not used.
RI
40
I
UART Ring-Indicator or general purpose input. This input has an internal pull-down resistor
and can be left unconnected when not used.
ANCILLARY SIGNALS (CMOS/TTL Voltage Levels)
XTAL1
14
I
Crystal or external clock input. This input is not 5V tolerant.
XTAL2
15
O
Crystal or buffered clock output. This output may be use to drive a clock buffer which can
drive other device(s).
PwrSave
13
I
Power-Save (active high). This feature isolates the L220’s data bus interface from the host
preventing other bus activities that cause higher power drain during sleep mode. See Sleep
Mode with Auto Wake-up and Power-Save Feature section for details.
ACP
16
I
Autosleep for Charge Pump (active HIGH). When this pin is HIGH, the charge pump is shut
off if the L220 is already in partial sleep mode, i.e. the crystal oscillator is stopped.
I/M#
4
I
Intel or Motorola Bus Select.
When I/M# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus type of
interface.
When I/M# pin is LOW, 68 or Motorola mode, the device will operate in the Motorola bus
type of interface.
RESET
(RESET#)
28
I
When I/M# pin is HIGH for Intel bus interface, this input becomes RESET (active high).
When I/M# pin is LOW for Motorola bus interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers and all outputs of
the UART. The UART transmitter output will be held HIGH, the receiver input will be ignored
and outputs are reset during reset period (see
C2+
C2-
20
21
-
Charge pump capacitors. As shown in
Figure 1, a 0.1 uF capacitor should be placed
between these 2 pins.
C1+
C1-
29
30
-
Charge pump capacitors. As shown in
Figure 1, a 0.1 uF capacitor should be placed
between these 2 pins.
VREF+
32
Pwr +5.0V generated by the charge pump.
VREF-
22
Pwr -5.0V generated by the charge pump.
VCC
33
Pwr 3.0V to 5.5V power supply. All CMOS/TTL input pins, except XTAL1, are 5V tolerant.
GND
6, 18, 27
Pwr Power supply common, ground.
-
PAD
Pwr The center pad on the backside of the 40-QFN package is metallic and is not electrically
connected to anything inside the device. It must be soldered on to the PCB and may be
optionally connected to GND on the PCB. The thermal pad size on the PCB should be the
approximate size of this center pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the PCB thermal pad.
NC
31
-
No Connect. Note that in Motorola mode, the IOR# pin also becomes an NC pin.
Pin Descriptions
NAME
40-QFN
PIN#
TYPE
DESCRIPTION
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